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Metastable 74ACT574

Carl Reese
Prodigy 230 points


Greetings:

I'm sure, from time to time, you get questions regarding unmet setup times or hold times.

I'm writing to ask what behavior occurs in a 74ACT574 if a given input does not meet the required setup time, or if a given input does not meet the required hold time.

Will the associated output settle into a known state within a given number of nanoseconds, or will the associated output go indeterminate for a prolonged timeframe?

I have an asynchronous input that must be clock-synchronized, and I'm not sure of the best approach.

You guys are the best!

Carl Reese

Metro Electronic Services, Inc.

214-794-4897 cell;

  • 0
    TI__Guru* 97066 points

    Carl,

    The setup time and hold time are related to the internal propagation delays of the part.  If the input to the flip-flop is unknown during any part of the input cycle (ie from the start of the setup time through the clock trigger until the hold time expires), then the output is also unknown.  That being said, the datasheet values are (generally speaking) heavily guard-banded and you will find that the part is more forgiving than the values would suggest.

    The output will maintain a valid logic level, but if the input is unknown there's no way to know _which_ valid logic level it has chosen without reading it or clocking through a valid input value.

    If you can provide a schematic and/or scope shots of the signals involved we can likely be of more help.