What would be the long term performance of +5V 74HCxx logic if two outputs in a single package have a bus contention condition? I was looking at a lab PCB with an incorrect resistor population resulting in 100 ohms between adjacent outputs in a single HC package + one downstream HC input. It has been running for months w/o issue, but this got me to wondering.
Normal output drive current is +/-6mA from looking at several 74HCxx datasheets. Scoping the downstream input shows +1.4V amplitude regions at 30% duty cycle when the two outputs drive opposing logic levels. At +1.4V, there are no errant VIH crossings for the downstream input, so functional performance has been fine. Should I expect to see a test failure if I let it run for several more months? A curiosity for me. Thanks!