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TXB0102DCUR design issue

I am using this chip to do voltage level conversion between 3.3v and 5v on the UART TX and TX l;ines.

I have two  questions .

1)  The datasheet is saying the following:

" To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to GND through a pulldown resistor and must not be enabled until VCCA and VCCB are fully ramped and stable"

I don't have an available GPIO to control OE .  can I use this chip in always "ebabled" and ready state  by pulling OE high ?

2) the datasheet is showing layout for multilayer boards  where the GND is placed on inner layers. I am only using double sided boards so what would be the layout for that ? 

also the by  pass capacitor is shown placed between the two pins .but the DCUR package pin distance is too narrow for any part placement between them.

I am showing the layout below please correct and advise.