SN*4LVC541A Octal Buffers/Drivers. I wish to use this chip to drive a low impedance with a 25 MHz square wave. If I parallel 4 gates together on input and output to try and gain as much current drive as possible, how much current can I get. e.g. If I wanted to drive 50 ohms to a full 3.3V output I would need 66 mA. If I wanted to drive 10 ohms I would need 330 mA. I suspect the first is acceptable and the second case is not. From the data sheet it appears that under absolute maximum ratings I could get 50 mA from one gate, and a maximum of 100 mA paralleling gates given the maximum Vcc and ground currents. Is this the correct interpretation of the specification? Thanks, Charles Robidart.