SN74LVC540 Logic Level details

Jeyalakshmi Kanniah1

Prodigy 170 points

Hi,

I am SN74LVC540APW device in my design and proto-boards testing are in progress.

The schematic is attached and the inverter IC pin connection details are below.

OE1*(pin1) & OE2*(pin19) tied to ground permanently.
Input pins are connected to Artix-7series FPGA device output.
When FPGA is not configured state, FPGA outputs are in tri-state.
In this case, what is output of SN74LVC540APW device?
In datasheet, there is no information for this condition

Issue:

We have 5-protoboards. In that I am seeing the difference in inverter behavior.
Case1: In board01, if the inputs are tri-state(low-measured using Oscilloscope) and the outputs are Low
Case2: In board02, if the inputs are tri-state(Low) and the outputs are high

Please let me know why the difference is happening and what is the cause for this problem?

Note: Part marking of the Devices are same.

Thanks,

Jeyalakshmi

over 9 years ago

0 Clemens Ladisch over 9 years ago

Guru 317800 points

All CMOS logic datasheets say:

All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

0 ShreyasRao over 9 years ago in reply to Clemens Ladisch

TI__Guru 62480 points

Thanks Clemens for your response .I appreciate your contribution and support.
Jeyalakshmi,

Inputs are not recommended to be tri-stated/floating/open . It could pick up random signals and cause malfunction on the output and also in extreme cases affect parts reliability .

Logic

Logic forum

SN74LVC540 Logic Level details