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SN74LVC2G74 Clock Triggering

Other Parts Discussed in Thread: SN74LVC2G74

Hi Community,

I am using this d-type flipflop with ¬Q and D connected. Clock input is a debounced push button with really slow rising edge and falling edge. Both PRE and CLR are pulled on high. So my flipflop converts the button into a switch. 

Can someone clarify what "Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse" (see SN74LVC2G74 Datasheet on page 1 "DESCRIPTION/ORDERING INFORMATION") really means?

Right now my Q follows the operation of the pushbutton but with harder edges (like a schmitt trigger without hysteresis). It triggers on both rising and falling clock edge. So if pushed Q is high and on release it's low.

I don't know why it's not working like expected. I thought it's positive edge triggered with no relation to my rise time, why is it changing Q to low on a falling clock edge?. 

orange = debounced pushbutton on clock input

green = Q of Flipflop

Thanks,

Stoane

  • Hi Stoane ,

    The output should not change with the negative edge of the clock and / or when inputs are toggled during high /low levels of the clocks . it seems that there is other interaction going on in the your system . Do you have Vcc , D plots lined up along with this which you can share ? I hope you have good bypass caps at the Vcc to avoid glitches etc.
  • 你好!
    我遇到了和你一样的问题。我想要实现的目的和你是一模一样的,当我按下开关时候,Q引脚为低,释放了就变高了;想不明白为啥,时钟的下降沿也能触发电平转换,你后来是怎么样解决的?能帮助我吗?