The SPEC of SN74AVC8T245 input transition rise or fall rate

This device does not have Schmitt trigger inputs, so SCBA004: Implications of Slow or Floating CMOS Inputs applies:

A slow input edge rate, coupled with the noise generated on the power rails when the output switches, can cause excessive output errors or oscillations. Similar situations can occur if an unused input is left floating or is not actively held at a valid logic level.

These functional problems are due to voltage transients induced on the device’s power system as the output load current (I_O) flows through the parasitic lead inductances during switching (see Figure 4). Because the device’s internal power-supply nodes are used as voltage references throughout the integrated circuit, inductive voltage spikes, V_GND, affect the way signals appear to the internal gate structures. For example, as the voltage at the device’s ground node rises, the input signal, V_I′, appears to decrease in magnitude. This undesirable phenomenon can then erroneously change the output if a threshold violation occurs.

In the case of a slowly rising input edge, if the change in voltage at GND is large enough, the apparent signal, V_I′, at the device appears to be driven back through the threshold and the output starts to switch in the opposite direction. If worst-case conditions prevail (simultaneously switching all of the outputs with large transient load currents), the slow input edge is repeatedly driven back through the threshold, causing the output to oscillate. Therefore, the maximum input transition time of the device should not be violated, so no damage to the circuit or the package occurs.

The datasheet (section 6.3) recommends a maximum Δt/Δv of 5 ns/V.
10000 ns/V is so far above this limit that bad effects are very likely.

Thank for your reply.

I'm sorry,I made a mistake.

The "10us/V" is not correct.
"10ns/V" is correct.

Best regards