Hi, I am using SN74LVC74ADRG4 as positive edge triggered D flip-flop in my application with output /Q directly feedback to D input. However, the output seems to be correct for the 1st clock (change state at rising edge and output is latched). The output become error when I apply subsequent clocks, it change state at both rising edge and falling edge, which mean output will toggle twice and final state become the same after each clock pulse. Can you advice how can this happen in positive edge triggered flip-flop? Thanks.