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SN74LVC74ADRG4 problem

Other Parts Discussed in Thread: SN74LS74A, SN74S374, SN74AHC174, SN74AUP1G74

Hi, I am using SN74LVC74ADRG4 as positive edge triggered D flip-flop in my application with output /Q directly feedback to D input. However, the output seems to be correct for the 1st clock (change state at rising edge and output is latched). The output become error when I apply subsequent clocks, it change state at both rising edge and falling edge, which mean output will toggle twice and final state become the same after each clock pulse. Can you advice how can this happen in positive edge triggered flip-flop? Thanks.

  • hi Joe ,

    I believe you are connecting this as frequency divider and would expect f/2 at the output . could you please share the schematic and also ensure that the setup / hold time is taken care of ? Is the input transition rate is taken care ?
  • hi Shreyas, thanks for your support. I am using it to detect power button on/off and control power button LED light (press on/ press off).

    Please refer schematic at below, the clock input will be pulled low by normally off button. When I press the button, it become open and clock signal pulled high by R376 until I release the button.

    with T(hold) around 70us:

    I have tried to add delay with buffer as below:

    And T(hold) was delay to 680us:

    However, it doesn't help. According to data sheet, the required hold time is only 1ns. Whereas setup time requirement is 3ns which is much less than my application.

    The flip-flop is working properly if I remove D input from Q output feedback and manually toggle the D input.

    Thanks for your support.

  • You might be violating the input transition time of the clock pin with the RC time constant from the pullups being higher than the recommended condition table specifying it to be 10ns/V . A Schmitt trigger device cleans up the slow signal into a square waveform .
    The hold time in uS (for data to be active after positive clock ) is more than enough for the device to work but I am certain that is not the issue you have . what is the setup time you have ? Can you give a zoomed in scopeshot of the clock and input pins ?
  •  Please refer the attachment or scopeshot of the clock and input pins. I will try to add schmitt trigger to clock input signal and make sure it fulfill  10ns/V spec. Will feedback later on the result. Thanks.

  • Hi Shreyas, I have successfully make the flip-flop working properly after adding Schmitt buffer to clock input. However, the best rise time I can get now is 244ns (rise from 0 to 3.3V) which is still much longer than spec requirement, probably due to wire connection or probe capacitance. Actually we are looking for 3.3V D flip flop to replace 5V D flip-flop SN74LS74A. This 5V flip-flop is working properly with initial circuit. I go through the datasheet again for SN74LS74A, there is no mention about input transition rise and fall rate like in SN74LVC74. But both datasheets also mention 'Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse' in the introduction description, which is a bit misleading that rise time of clock pulse is not critical. Can you recommend a 3.3V D flip flop with Schmitt trigger action at all inputs so that it can tolerate slower input rise and fall times? Thank you very much for your prompt support.

  • Hi Joe ,

    I am glad to hear it worked right . I searched in our portfolio and there are Schmitt trigger input in SN74S374 which unfortunately operate at 5Vcc . I can only recommend sn74AHC174 which are more tolerant for slower input transition rates . I will also take note of having a Schmitt trigger flip flop in our portfolio as backlog .
  • Hi Joe ,

    Also SN74AUP1G74 seems to be better suited with 200ns/V transition rate . hope this works better . Let me know .
  • Hi Shreyas,

    Thanks for the recommendation. I will consider sn74AHC174 and SN74AUP1G74 as the replacement part.

    Thanks again for your support on resolving this issue.