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SN74LVC1G123YZPR max rise time specification of CLR_N input (non Schmitt)

Steffen Griehl
Prodigy 20 points

Hi,


looking at the data sheet (REVISED JUNE 2015) , I'm missing the max rise time specification.

Need this info for a big project, can someone help out here please?

Thanks a lot

Steffen

  • 0
    Guru 316690 points

    This is probably the same as for all the other devices in the LVC family, i.e., 5 ns/V for 5 V, 10 ns/V for 3.3 V, 20 ns/V for 2.5 V and 1.8 V.

  • 0 in reply to Clemens Ladisch
    Prodigy 20 points

    Thank you.

    Is that really a limit like a max rating or just a recommended operating?

    What else than the increase current consumption is expected when violating 20ns/V at 1.8V?

    My problem: The rising CLR_N (tr=30µs) doesn't trigger the output, whereas tr=30ns does it.
    I would expect an output trigger at any transition time. Are there other reasons preventing an output trigger?

    regards Steffen

  • 0 in reply to Steffen Griehl
    Guru 316690 points

    The recommended operating conditions guarantee that the device works.
    The absolute maximum ratings guarantee that the device does not go up in smoke immediately.

    A too-slow rise time typically results in oscillations in the output (see Implications of Slow or Floating CMOS Inputs (SCBA004) for details). In the case of a clock signal, these oscillations might be too fast for the rest of the circuit, so the behaviour of the device will be entirely unpredictable.