Hi team,
I understand SN74AVC1T45 supports partial-power-down application using Ioff circuitry, when either VCCA or VCCB is at GND level. Also in the datasheet, it is recommended to power up VCCA followed by VCCB, which is because DIR is with reference to VCCA and the recommended power up sequence is for defined logic for DIR.
Q1: when will device exist partial-power-down? VCC > 10mV? VCC > 100mV? VCC > 500mV? I assume the threshold should be below 1.2V, which is min operating voltage for VCC, but would like to know the threshold.
Q2: Assuming DIR pin is short to GND, under normal operation, A is always output and B is always input, i.e. B --> A always. During power up, VCCB is already powered up and VCCA is coming up from low to high, is there any risk that A --> B? Please note DIR is always shorted to GND (i.e. a clear defined '0' even if VCCA is still ramping, true?).
Q2: Assuming DIR pin is '1', under normal operation, A is always input and B is always output, i.e. A --> B always. During power up, VCCB is already powered up and VCCA is coming up from low to high, is there any risk that B --> A? I guess that is the scenario to prevent.
