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SN74AVCH8T245 - Can I use this translator to support RGMII?

Other Parts Discussed in Thread: SN74AVCH8T245

Hi,

I calculated ICCB maximum for SN74AVCH8T245RHLR voltage level translator as per the following equation:

ICCB = static ICCB + dynamic ICCB

as per the following link

The maximum ICCB current as per my calculation was 92.4mA for 250MHz frequency.

The absolute maximum current through ICCB is 100mA.

The frequency I have chosen is wrt RGMII LVCMOS interface.

Is there any problem , because the absolute maximum and calculated ICCB is really close?

Can I use SN74AVCH8T245RHLR for level translating RGMII signals?

Regards,

Bhavya

  • Bhavya,

    That amount of current draw through the VCCB pin (92.4 mA) is within the acceptable limits of the SN74AVCH8T245 (100 mA). However, you mentioned that you intend to operate the device at a frequency of 250 MHz, which is not supported. The maximum supported clock frequency is 160 MHz.

    Do you need 250 MHz operation?

    Best Regards,
    Nirav

  • Bhavya,

    I am intereted in understanding your application. Why is it neccesary to operate at 250 MHz? Can you share some details with me? Thanks.

    Best Regards,
    Nirav
  • Hi Nirav,

    For RGMII maximum clock frequency is 125MHz. But the data rates will be double of clock frequency

    320Mbps(Mega bit per second) is mentioned in the datasheet.Is this the data rate per channel of level translator? For             example 320Mbps for A1 to B1 pin translation?

    Please let me know if we can use the part number for RGMII level translation.

    Regards,
    Bhavya

  • Bhavya,

    I read the RGMII Version 2.0 specfication. I do not believe that the data channels would operate at 250 MHz if the clock channel operates at 125 MHz. Instead, the data channels would operate at 250 *Mbps* (or 125 MHz as expressed in frequency).

    Clock frequency = Number of cycles per second
    Bit Rate = Number of bits per second
    One clock cycle carries two bits (Positive Bit, Negative Bit)

    This means that Bit Rate = 2 * Clock Frequency

    The timing diagram below is taken from the RGMII specification (text in green and red is my addition):


     
    TXC is the transmit reference clock. It operates at a maximum frequency of 125 MHz. This corresponds to a maximum bitrate of 250 Mbps (125 M cycles/second)*(2 bits/cycle).

    TXD is the group of 4 data channels. Notice that there is one bit transmitted with the rising edge of TXC, and one bit transmited with the falling edge of TXC. So in one clock cycle, TXD also transmits 2 bits. This is identical to TXC.

    In short, you can use the SN74AVCH8T245 to support the maximum data rates in RGMII.

    Best Regards,
    Nirav