Hello,
Please see CD54HC4538 truth table below and datasheet located at www.ti.com/.../cd74hc4538.pdf.
What is the Q and Qn for the following input conditions.
Rn A Bn Q Qn
H L H ? ?
Stephen
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Hello,
Please see CD54HC4538 truth table below and datasheet located at www.ti.com/.../cd74hc4538.pdf.
What is the Q and Qn for the following input conditions.
Rn A Bn Q Qn
H L H ? ?
Stephen
Hello Dennis,
How did you come to that conclusion?
I had difficulty using the Logic Diagram (Figure 2) and the Flip Flop diagram (Figure 1) to come up with an answer because I wasn't sure what some of the components were. For example, what is the device that has a P and N in the flip flop diagram? Also, how does the P-channel FET work without the source connected to the substrate?
Stephen
Hi Steven!
Sorry, did not have a chance to respond earlier. I didn't have a look at the flip flop diagram, only the truth table. The device outputs a high pulse on Q (low pulse on Qn) when A is low and Bn has a high->low transition or when Bn is high and A has a low->high transition. This means that having A low and Bn high will not trigger anything, so Q is low and Qn is high. Bn would have to go from high->low to start a high pulse on Q. Similar for Bn high and A low - Q will be low until A transitions from low->high.
Dennis