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TXS0108EZXYR.

Other Parts Discussed in Thread: TXS0108E

Hi team,

My customer wants to use TXS0108EZXYR.

But they have some questions:

  1. How the chip can support the open-drain and push-pull? (The open drain and push-pull are decide by the circuit behind?) Can it be used for I2C function?   ( I think yes, could you please help explain why the chip can support open-drain and push-pull).

  2. If they use it as the level shift for 3.3v to 1.8v for 27Mhz clock, does it have some problems for clock level shift function?

  3. The chip has internal pull up resistor, if the I/O behind is high resistance state, so the pin is high level here, right?

Thank you.

BR

Frank

  • Frank - My feedback is below:

    Frank Xiao said:

    How the chip can support the open-drain and push-pull? (The open drain and push-pull are decide by the circuit behind?) Can it be used for I2C function?   ( I think yes, could you please help explain why the chip can support open-drain and push-pull)..

    Yes the open-drain/push-pull support refers to the interface of the peripheral IC connected to the TXS0108E. It can be used to support I2C. This app note explains the architecture of our TXS translators, including their ability to support open-drain ICs and push-pull ICs.

    Frank Xiao said:

    If they use it as the level shift for 3.3v to 1.8v for 27Mhz clock, does it have some problems for clock level shift function?

    With VCCA = 1.80V and VCCB = 3.30V (remember that VCCA <= VCCB), TXS0108E can support datarates of up to 60 Mbps, equivalent to a 30 MHz clock. Keep in mind that for larger capactive loads (> 70 pF), the AVC/LVC translators would be a better choice.

    Frank Xiao said:

    The chip has internal pull up resistor, if the I/O behind is high resistance state, so the pin is high level here, right?

    Yes that is correct. If both side of the TXS0108E I/O are left open (e.g. A1 and B1 are both left open), then the I/Os will be set to Logic High.

    Best Regards,
    Nirav