SN74LV165ARGYR QH Output Wrong Value In A Cascade Design

Yang chiayi

Other Parts Discussed in Thread: SN74LV165A

Hello,Sir

We have a cascade SN74LV165ARGYR design is eigth-74LV165A network constructed from a series of SN74LV165ARGYR. In our circuit, CLK INH is always pull 1K resistor to ground. We don’t implemented CLK INH feature. And VCC 3.3V and CLK is 2.667MHz.

When parallel inputs are static, we got SN74LV165ARGYR output (QH) wrong value question from the signal waveform and LA analysis result, but it only happened on the 8th one that 8^th QH (=7^th SER) series value became to “7C” from “6C” random and the issue may not happen continued. But add 8PF capacitor or Active probe touch on SN74LV165ARGYR Clock source, the issue will not happen again.

Attached are the circuit/routing topology, signal waveform and LA analysis.

In the normal and abnormal SGPI waveforms, 7th 74LV165 (/LD, CLK, SER) and data in (“E”, pin3) is on the 8th one. You can see SER of 7th 74LV165 (= 8th QH output) become 7C value when the parallel data in (“E”, pin3) on the 8th one is static.

Whatever normal/abnormal waveform, we also saw 8th QH start data output series data when /LD is still low level; QH output data should on the 1st CLK rising edge after /LD is high level.

Please kindly check the question and review the design.

over 8 years ago

0 Joe Stephan over 8 years ago

TI__Intellectual 2050 points

Hello Yang,

Thank you for providing a lot of details and waveforms.

I want to clarify a few things.

The problem is that the serial value is randomly changing from “6C” to “7C”, and this only happens for the 8th LV165 device, correct? Also, is this problem only happening in the LA analysis?

Is “6C” the desired serial value? If so, then based on the Normal/Abnormal waveforms it looks like the Normal waveform is correct and the Abnormal waveform is incorrect. Also, the Abnormal waveform is with the capacitor/active probe touch?

Regards,
Joe

0 Yang chiayi over 8 years ago in reply to Joe Stephan

Prodigy 70 points

Hi Joseph

Thanks for getting your response. My answer is as below;

The problem is that the serial value is randomly changing from “6C” to “7C”, and this only happens for the 8th LV165 device, correct?

=> Yes.

Also, is this problem only happening in the LA analysis?

=> No, it is also captured by LeCroy 204MXi Oscilloscope, you can see the SGPI normal (01101100=6C) / abnormal (01111100=7C) waveforms.

Is “6C” the desired serial value? 
=> Yes, 6C is the serial value meaning 01101100.

 
If so, then based on the Normal/Abnormal waveforms it looks like the Normal waveform is correct and the abnormal waveform is incorrect. 
=> Yes

Also, the abnormal waveform is with the capacitor/active probe touch?
=>  No, the abnormal waveform is without capacitor/active probe touch. Either add 8PF capacitor or Active probe touch on the 8

^th

 SN74LV165ARGYR Clock source won’t happen the serial value is randomly changing.

0 Peter Chen(ICP_FAE) over 8 years ago in reply to Yang chiayi

TI__Intellectual 2480 points

Is there any feedback after the detail issue descriptions?

0 Joe Stephan over 8 years ago in reply to Yang chiayi

TI__Intellectual 2050 points

Yang,

Thank you for your response and for your patience.

You mention that 8th QH outputs series data when /LD is still low level, which is only happening for the 8th device. You can try using the CLK Inhibit on the 8th 'lv165 until after /LD is back to high level. This should stop the ouput series data from starting while /LD is still low.

Could you provide a waveform for the 7th 'lv165 device, similar to how you captured the 8th 'lv165 device?

I am curious, have you tested this for multiple boards? Also, have you tried replacing the 8th 'lv165 with another one you have?

Best Regards,
Joe

0 Yang chiayi over 8 years ago in reply to Joe Stephan

Prodigy 70 points

Joe,

I’d like to clarify 1st to 8th 74LV165A logics are all the same timing waveform for “QH outputs series data when /LD is still low level”. You can see the waveform of 7^th 74lv165A.

CLK Inhibit pull down design will affect 8th 74LV165A QH output is randomly changing from “6C” to “7C” ?

For more researching, I measured 7 pieces PCBAs with the same PCB revision, they are two TI making codes and the detail as the IC making picture.

I believe this is not single case for component issue. Please help to figure out the possible root cause.

Below is the waveform for the 7th 'lv165 device.

0 ShreyasRao over 8 years ago in reply to Yang chiayi

TI__Guru 62200 points

Hi Peter , Yang ,

At this time , after discussing with the team internally , we are unsure on why the random behavior could be happening.
The fact that adding a small cap or active probe(which will load the line with tiny cap) resolves the issue points to be some glitch on the clock lines which is being smoothed out.
however , when you say that particular lot code doesn't have this issue compared to another points to some issue with Z220 lot.
you could test out each good PCB by replacing the abnormal device(and it should fail) and replacing the bad PCB by the good device(it should work) to ensure and isolate the bad lot of devices. To again isolate the E input , can toggle between high and low on it. Toggle high and low on all other inputs to figure any abnormality .
Just to add that 48 indicates the Year and month (2014 / Aug) of manufacture and D5VT is the lot trace code.
If you could initiate Failure return to us , we can take further look into the device on ATE(tester) to see if all parameters are good.

0 Yang chiayi over 8 years ago in reply to ShreyasRao

Prodigy 70 points

Hi Shreyas,
I’d like to ask some questions first, please help to check them.

1. I saw 1st~8th 74LV165A logics are the same timing waveform which “QH outputs series data when /LD is still low level”. You can see the waveform I already attached. Is it the correct timing of 74LV165A ?
2. Is there specific clock requirement for glitch/rising/falling or others?
3. Is there known Errata for 74LV165A ?

0 ShreyasRao over 8 years ago in reply to Yang chiayi

TI__Guru 62200 points

Hi Yang ,

we discussed and looked into the transition time violation for the signals , setup or hold time violation which is most likely ruled out. With the same signals, the other 3 boards working probably rules out the timing issues.
There is no errata for sn74LV165A since this is the first for the device to be receiving the issue.

0 Yang chiayi over 8 years ago in reply to ShreyasRao

Prodigy 70 points

Hi Shreyas,

Thanks for your replying.

After some tests, the random behavior should change with Z220 of the lot trace code.

Below is the test configuration and result.

0 ShreyasRao over 8 years ago in reply to Yang chiayi

TI__Guru 62200 points

Hi Yang ,

From what I could understand from your experiments indicates that the failures are moving with the lot trace code(Z220) and not board related as suspected .Please confirm.
I have informed our FA /CQE about this.

0 Yang chiayi over 8 years ago in reply to ShreyasRao

Prodigy 70 points

Hi Shreyas,

As the test result on the picture, I did these tests on the two boards (PCBA SN 352, 986) for this 8^th LV165 randomly changing related with Z220 and D5VT of lot trace code test.

In original status, the failures is when Z220 on 8^th LV165 of PCBA SN 352 and it is good when D5VT is on 8^th LV165 of PCB SN 986.(Test 1)

After exchange the 8^th LV165 IC between the two boards, it is good when D5VT is on PCB SN 352. (Test 2)

But, the failures is Z220 change to PCBA SN 986.

Again, exchange back the original status. The failures is Z220 that change back to PCBA SN 352 and it is still good when D5VT is on 8^th LV165 of PCB SN 986. (Test 5)

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SN74LV165ARGYR QH Output Wrong Value In A Cascade Design