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CD4013BE

Thong NGo
Prodigy 30 points
Other Parts Discussed in Thread: SN74LVC1G17, SN74LVC1G14

I use CD4013BE for my design and I am having these questions, please help:

I use only half of the CD4013BE: 

Pin 1: Q

Pin 2: Q_bar

Pin 7 and Pin 14: GND and VDD +12VDC respectively

Pin 3: Clock

Pin 5: Data

Pin 4, Pin 6: Tied to GND

The output Pin 1 Q and Pin 2 Q_bar is tied to my circuit consisting of a simple 2N3906 transistor.   The base of the transistor I put a 22KOhm between the output pins (1 for Q and 2 for Q_bar), the Emitter of the 2N3906 is tied to a 10Kohm to GND.    The collector of 2N3906 is connected to an red LED with about 1KOhm resistor to VCC.   What I want to do is when ever the output of Pin 1 Q is set, the LED is ON telling me something, for example something that is wrong.   The same is for Q_bar output, if the 2N3906 circuit turn on my other green LED, I know everything is normal.      In general, my circuit works but i see intermittent sometimes.  What is mean by "intermittent" is that sometimes both of the LED blinks which I can not tell whether or not something is wrong or right.   The CLOCK input to Pin 3 of the CD4013BE is from a rotating disc (wheel)  and an Optical Slot (interrupter) to detect the revolution of my small DC motor when ever the wheel passes by the Optical slot hence giving me the CLOCK signal.     The DATA pin 5 is from my other input signal I want to compare.

Should the IC's all other pins be tied to GND too?  The problem I have is intermittent.  I sometimes see the Output of Q and Q_bar on at the same time but they are not supposed to be.   Is that could be my timing between the CLK and DATA or no?.  Please help and any suggestion to improve my circuit is appreciated.

  • 0
    TI__Guru 62240 points
    Hi Thong ,

    I would suggest the unused input pins to be tied to known rail. Gnd would work.
    Having Q, Q\ on at the same pin is unusual I agree . how sharp is the rising edge inputs on the clock and the data ? having noisy inputs can cause double clocking , would be best to have a Schmitt trigger buffer before the clock /data .
  • 0 in reply to ShreyasRao
    Prodigy 30 points
    Hi Shreyas Rao,
    The edges of my CLOCK pulse and the Data is very small, less than 100-500ns. If I use a Schmitt trigger as you suggest, but if I do that my signal will reversed? Can you please explain this a little more? for example, if I use Schmitt trigger both , the CLOCK and DATA, then both of them will be reversed? because the Schmitt trigger is an inverter? I'm not sure about this.
  • 0 in reply to Thong NGo
    TI__Guru 62240 points
    Hi Thong ,

    100-500ns may be significant enough to cause troubles many times . The LVC , LVT aLVC, ABT etc have very low threshold on input transition rate of ~10ns /V.
    Schmitt trigger inputs have slightly different architecture internally to guarantee different threshold voltage on LH / HL transition which helps in well defined hysteresis & noise immunity.
    They are Schmitt trigger inverters(SN74LVC1G14) as well as Schmitt trigger buffers (SN74LVC1G17) and also many gates with Schmitt trigger inputs .
    Let me know what you find out .