SN74LVC1G80 Initial state and the Q0 mean?

user4191200

Other Parts Discussed in Thread: SN74LVC1G80

Hi, Sir:

I have seen that it is a D-type filp-flop device which will change state in the CLK's rising edge. Right now I want to ask you a few questions:

1. while the device is power on and CLK is in "L" state which is not have the rising edge, How the state of the output pin /Q will be ?

2. while the clk is "L " and no matter what the Input D port be, the output /Q =Qo. Is that mean the /Q port will keep the value of the previous time while the clk port dosen't have rising edge?

over 8 years ago

0 Clemens Ladisch over 8 years ago

Guru 318050 points

The initial state is undefined; see Power-Up Behavior of Clocked Devices (SCHA005).

As long as the clock stays low, the output is the state that the input had at the last rising edge.

0 user4191200 over 8 years ago in reply to Clemens Ladisch

Prodigy 20 points

if i ha

Clemens Ladisch said:

The initial state is undefined; see Power-Up Behavior of Clocked Devices (SCHA005).

As long as the clock stays low, the output is the state that the input had at the last rising edge.

We designed a pull-down resistor on the output port Q. While the circuit is in the power on state , CLK='L' , /PRE and /CLR port ="H", the output port Q will be Q=Qo="L"?

0 Clemens Ladisch over 8 years ago in reply to user4191200

Guru 318050 points

A pull-down resistor would be useful only if the output were floating. But it's not, it's actively driven to either a high or low state (you don't know which).

And the SN74LVC1G80 does not have P̅R̅E̅ or C̅L̅R̅ inputs.

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SN74LVC1G80 Initial state and the Q0 mean?