generating a low-skew complementary signal (i.e. alternative for 74265)

Stefan Tauner

hello

i am wondering how one would create a clean TTL (or CMOS) signal and its complementary signal with a low skew. there was a logic ic, that would do that but is now obsolete: 74265

(ideally the solution in my case would be available in a SOIC14 (or less pins) package)

the background of my question can be read here: http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/55838/198132.aspx (but the second message gets verified by stranger(s) without it answering this aspect)

thanks!

over 15 years ago

0 Chris Cockrill over 15 years ago

TI__Mastermind 46480 points

Can you use a flip flop Like LVC1G74? http://focus.ti.com/lit/ds/symlink/sn74lvc1g74.pdf

0 Stefan Tauner over 15 years ago in reply to Chris Cockrill

Prodigy 40 points

no, i can't use a clocked device since this would delay the generated output and would probably introduce metastability problems (if clock and input is the same signal) or i would have to create a new clock.

i have not looked into various PLLs, but as far as i know they need some time to get going, so this is no option for me either (because this clock is only used temporarily to synchronize a few (=40) bits (transfered via spi).

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generating a low-skew complementary signal (i.e. alternative for 74265)