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SN74125: OE# pin frequency characteristic of SN74LVC1G125 IC.

Srinivasuki Murugesan
Prodigy 30 points

Part Number: SN74125

I am using SN74LVC1G125 in my design. The OE# pin of the buffer is driven using a clock pulse and the input Pin A is always at 0 (grounded). The output Y has a pull-up resistor of 10K. Hence when the frequency of the clock pulse driving OE# signal is more than 200KHz, the output Y is always zero. Let us know the reason for this. Whether the OE# will not work beyond 200KHz and let us know the frequency characteristic of this IC with respect to OE# input

DATA_LATCH signal is driven by a 400KHz clock pulse. And the Output Y is always zero in the below circuit

  • 0
    TI__Guru* 97046 points
    Hi Srinivasuki,

    Your circuit didn't make it through -- the best way I know to post a picture is to save it and then insert it in your post (sometimes the pictures on this forum are a bit buggy).

    From your description, it sounds like you need an open-drain inverter. Have you considered using an SN74LVC1G06 instead of the '125?

    The SN74LVC1G125 will enable/disable the outputs in <10.1ns. When you have the output disabled, the device will be in 'high impedance' mode and the output waveform will be subject to RC time constants for rise/fall times. It is likely that your load capacitance and pull-up resistor are sized such that they cannot pull up the signal to Vcc in the time allowed. My first recommendation would be to use a smaller pull-up resistor.
  • 0 in reply to Emrys Maier
    Prodigy 30 points

    I have attached circuit diagram and also the waveform captures for your reference.

    The input signal given to the OE# pin is DATA_LATCH signal which is low for only 20 ns and high for about 2.54us and the cycle continuous.

    When the DATA_LATCH signal is high, the output Y is LOW.

    But when the DATA_LATCH signal is Low, the expected output at pin Y is HIGH. But in our circuit, the Output at pin Y is LOW only.

    We wanted to understand the reason for this behavior. And the proof from datasheet that this behavior is as per the device characteristics.

  • 0 in reply to Srinivasuki Murugesan
    Prodigy 30 points
    For the above circuit, Let me know the below parameters for the buffer SN74LVC1G125

    1. The Rise time/Fall time of the output pulse
    2. The OE# to Output propagation delay.
    3. The TI recommended circuit of the above described.
    4. The recommended pull-up resistor value
    5. My circuit is operated around 500KHz, whether the buffer will support.
  • 0 in reply to Emrys Maier
    Guru 316150 points

    it sounds like you need an open-drain inverter

    That circuit is an open-drain buffer.

    Anyway, the output signal does not change because of C10. Such a decoupling capacitor must go between VCC and GND instead.

  • 0 in reply to Clemens Ladisch
    TI__Guru* 97046 points

    Thanks Clemens,

    You're right, I had the wrong picture in my head from the description.  An open-drain buffer like SN74LVC1G07 would work - but from the circuit, I'm not sure why an open-drain configuration is being used at all.  Two solutions come to mind - one is eliminating the buffer entirely, and the other is using it in its normal configuration.

     

    To take your questions one at a time Srinivasuki,

    For the above circuit, Let me know the below parameters for the buffer SN74LVC1G125

    As Clemens mentioned, I would move that capacitor to go from Vcc to GND instead of Vcc to Y.

    I would also connect OE\ to ground and your input signal to A, then remove the pull-up resistor on the output.  This will change the output to a push-pull, and will improve your signal quality.

    1. The Rise time/Fall time of the output pulse

    In an open-drain configuration, the fall time will be very fast (on the order of <10ns), but the rise time will be related to your pull-up resistance and output line capacitance.  As the circuit stands now, you should expect to see a rise time around 4*10E-9*12E3 = 480 us.  That 10 nF capacitor is killing your output.

    If you only remove the 10nF capacitor, as an estimation, I would give ~10pF to the output load, so the rise time would be ~4*10E-12*12E3 = 480 ns.

    If the circuit is changed as I suggested above, you would see similar rise and fall times around 10ns each.

    2. The OE# to Output propagation delay.

    This is listed in the datasheet under 'Switching Characteristics' as t_en and t_dis (enable time and disable time).

    For 3.3V, you can expect a maximum delay of 5.3 ns for enable, and 5 ns for disable.

    3. The TI recommended circuit of the above described.

    Please see above description.  If you need a schematic, let me know and I will be happy to provide one.

    4. The recommended pull-up resistor value

    I would recommend using the device in the push-pull mode, so the pull-up resistor can be removed.

    5. My circuit is operated around 500KHz, whether the buffer will support.

    Absolutely.  This buffer can operate easily beyond 100 MHz, so 500 kHz is no problem.