SN74AVC4T774: As a bus buffer

Toshiyuki

Hi,

Customer would like to use SN74AVC4T774 such as shown in the figure below. Would you please provide the information of skew for each output ?

condition : Vdd=1.8V, Data rate = 100Mbps

Best Regards,

Toshiyuki

over 9 years ago

0 aozer over 9 years ago

TI__Mastermind 31825 points

Hello Toshiyuki,

All of our logic devices are guaranteed to have a maximum skew of 1ns across equal loads.

0 Toshiyuki over 9 years ago in reply to aozer

Mastermind 7075 points

Hi aozer -san,

Thank you for the reply. Is there a application note for channel to channel skew ?

Best Regards,

Toshiyuki

0 aozer over 9 years ago in reply to Toshiyuki

TI__Mastermind 31825 points

Hello Toshiyuki,

The only application note I could find about skew is here:

Defining Skew, Propagation-Delay, Phase Offset (Phase Error)

Unfortunately, I could not find an application note that mentions specific skew values for our different logic families.

0 Toshiyuki over 9 years ago in reply to aozer

Mastermind 7075 points

Hi aozer-san,

Then, do you have the channel to channel skew measurements ?

Best Regards,

Toshiyuki

0 aozer over 9 years ago in reply to Toshiyuki

TI__Mastermind 31825 points

Hello Toshiyuki,

Unfortunately, we do not have any specific measurements for channel to channel skew of our devices.

Because the SN74AVC4T774 is a CMOS device we can safely assume that the channel to channel skew will remain under 250ps, assuming equal loads on all outputs. However, generally 1ns is the standard rule of thumb.

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SN74AVC4T774: As a bus buffer