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TS3DDR4000 logical level translation

psir
Prodigy 50 points
Other Parts Discussed in Thread: TS3DDR4000Adam,

Could you confirm if port A, B &C could have different SSTL I/O levels? Can It support configuration of POD_12/SSTL_12 on port A and SSTL_18 on port B/C?
  • 0
    TI__Mastermind 45575 points

    Psir,

    The TS3DDR4000 is an unbuffered, bidirectional, passive FET switch where the signal path can be ideally modeled as a 0 ohm wire.  If you have the A channel selected to go to the B channel you cannot have different logic levels on the A and B path because they would be basically shorted together. 

    However, you can have different logic levels on the B and C channels and use the TS3DDR4000 control signals to select which channel be present on the A path.  The only issue I see with this is that there could be a moment <65ns where the B and C paths could be connected together as the TS3DDR4000 switches between B and C channels.  To avoid this situation where the B and C channels could be connected you can look for a signal switch with the break-before-make feature.  This features ensures that the signal path will be disconnected for some specified time before connecting the other signal path to avoid the un wanted contention. 

    Thank you,

    Adam

       

  • 0 in reply to Adam Torma
    Prodigy 50 points
    Adam,

    Thanks for the update. This won't work me. I am looking for a part to translate SSTL_18 to SSTL_12.
  • 0 in reply to psir
    TI__Mastermind 45575 points
    Psir,

    I'm not familiar with SSTL_18 and SSTL_12. Is SSTL_18 = 1.8V signals and SSTL_12 = 1.2 V signals? I will move this thread to the voltage translation and level shifting forum for help with your translator solution.

    Adam
  • 0 in reply to Adam Torma
    Prodigy 50 points
    Yes, you are right with voltage decoding.