• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 21 subscribers
  • Views 1668 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TXS0102: Levle shifter I2C compatibility with DM3730 processor

Petar Horvatic
Prodigy 190 points

Part Number: TXS0102
Other Parts Discussed in Thread: DM3730

We are using TXS0102 to level shift 1.8V I2C signal coming from master(DM3730) and on some boards we are not seeing the I2C clock on the output of level shifter.

Based on datasheet for TXS0102, inoput sI2C low signal has to be < 150mV.  Based on DM3730 datasheet, at higher sink currents master clock low can be as high as 360mV.  

Could someone confirm if these two parts are compatible?

  • 0
    TI__Guru* 97666 points

    Hi Petar,

    Can you share a schematic of your circuit?  We just need to see what all is connected to the TXS0102 to give the best answer.

  • 0 in reply to Emrys Maier
    Prodigy 190 points

    Schematic has 19 pages and 4 separate I2C buses all driven by the processor at a 1.8V I2C Level.   It is just not feasible to put everything up here.  I traced the particular problem of no clock on the 3.3V side of I2C3 to a blown ESD diode, D33 see below.   When i took that out , clock came back.    But my specific question is about I2C low thresholds.  processor can sink 3mA, and during that amount of current flow, clock signal low  level that he is responsible for, can be as high as 360mV.    Level shifter datasheet says it needs low signal to be < 150mV for it to work.  Is that a problem?  I understand that external pull up is not needed with TXS0102, and I did find on the schematic that they used multiple 10K pullups on the same line.  I will certainly recommend that it be removed.

  • 0 in reply to Petar Horvatic
    TI__Guru* 97666 points
    Thanks for the detailed schematics, this is very helpful.

    The multiple parallel pull-ups will add a lot of sink current for the 'low' state of the processor. I would recommend removing all of the external pull-ups and it will likely fix the problem.
  • 0 in reply to Emrys Maier
    Prodigy 190 points

    We have removed the un-necessary pull-ups.    However my question remains.  DM3730 processor can sink 3mA, with I2C signal low  level  as high as 360mV.    Level shifter datasheet says it needs low signal to be < 150mV for it to work.  Is that a problem?

    Levelshifter Datasheet

    Processor datasheet:

  • 0 in reply to Petar Horvatic
    TI__Guru* 97666 points

    If your sink current requirement is significantly below 3 mA for the processor (which it should be), then the output of the processor should also be significantly lower than the datasheet spec of 360 mV (typically, a CMOS output will drive very close to the rail if you aren't close to the VOL current rating).

    So, the first part of my answer is that I think the processor's output will be below the required VIL of the translator, which eliminates the problem entirely.

    Secondly, the translator indicates 150 mV as the VIL requirement specifically so that we can spec VOL at 400 mV. The way this device works, the output voltage (in the LOW state) will _always_ be higher than the input voltage. The amount is related to how much current is being sunk through the TXS device.

    So, the second part of my answer is that the translator will continue to function even if the input is above 150 mV, however the VOL will no longer be guaranteed to stay below 400 mV.

  • 0 in reply to Emrys Maier
    Prodigy 190 points
    Thank you, yes it does.