• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 20 subscribers
  • Views 1381 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

FIFO Architecture, Functions, and Applications

PieterT
Intellectual 640 points


Good day,

I have a question on the explanations provided by:  on FIFO devices.

It seems that metastability is quite a big problem with these devices although as I have noted from the application note, it only occurs in asynchronous operation? I will be operating in asynchronous mode, as I'll be interfacing an MCU to an ADC that operate at different clock speeds. What can I do to avoid metastability?

Can FIFO devices read and write at the same time or are these events that need to take place sequentially? I'd like to have data read in as I'm sending it out. If this is not possible will I have to read faster than I'm writing?

Thanks in advance for any help 

  • 0
    TI__Guru 62930 points
    Ian,
    The metastability issue is solely due to the asynchronous usage. When operating synchronously, there are no opportunities to violate setup/holds on registers/flops.
    You can read and write concurrently, as long as there is data in the FIFO to read. This can be determined/monitored with the flags.

    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    Intellectual 640 points

    Good day Wade,

    Thank you for the quick response.

    This does worry me in a sense as I will be working at an asynchronous state. My ADC's will be working faster than my MCU. I will therefore have to work at different clock frequencies. As a designer do I have to worry about meta-stability or is this something that the designer of the FIFO logic block already compensated for? If I have to account for it, how would I do so? I want to have an accurate data acquisition circuit and meta-stability seems like it could be a big problem.

    Thank you in advance for any help

  • 0 in reply to PieterT
    TI__Guru 62930 points
    Ian,
    The design teams that created these FIFOs are not longer available. However, if you can give me some more information it might help me answer more definitively. Can you can let me know what FIFO your are interested in? Write and read frequencies? If you are clocking in the data with a write clock, and not violating setup/hold on the input data, then you will not see any issues with data written to the FIFO. Most of the issues will be related to flags.
    This is the example shown in the app note you referenced. There is some metastability related to the generation of the empty flag.
    If you can manage the data without running it completely full or completely empty then you should not see issues with metastability.
    Regards,
    Wade