Hi Sir
I have a question about SN74AUP2G34 internal architecture.
May I get internal architecture at SN74AUP2G34 as below(like other logic series)?
Since I don't see it in datasheet. Thank you for your great support.
Hello Hugo,
Short answer: The SN74AUP2G34 has clamp diodes on the negative side of the input and output, but no diodes on the positive sides.
More details:
The input and output clamp diode structure of our devices is hidden in the Absolute Maximum Ratings table -- you just have to know how to decipher it.
The important parameters here are IIK and IOK (input and output clamp current).
Note that, in the above table, IIK is only defined for VI < 0. This means that there is a clamp diode on the negative side of the inputs, but not on the positive side.
Also, IOK is only defined for VO < 0, indicating that there is only a negative clamp diode on the outputs as well.
If these values are not listed in the datasheet, the next indicator would be VI and VO, the input and output voltage range. Here you can see that VI is listed as -0.5 to 4.6V. The negative value, -0.5V, indicates a negative clamp diode (the diode turn-on voltage is ~0.5V). The positive value, 4.5V, is independent of VCC, which indicates no positive clamp diode (if it had a positive clamp diode, the value would likely be VCC + 0.5V).
The same is true for the output voltage _with the exception of the output voltage range in the high or low state_. The output voltage range in the high or low state will usually indicate that the output should not be driven above VCC + 0.5V due to the pMOS being active in the push-pull CMOS output.
