The Function Table for the SN74LVC2G74 does not include the state where /PRE = H, /CLR = H, and CLK = H, (D can be X). Can you provide the outputs (Q and /Q) for this state?
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The Function Table for the SN74LVC2G74 does not include the state where /PRE = H, /CLR = H, and CLK = H, (D can be X). Can you provide the outputs (Q and /Q) for this state?
This is described outside the table:
When PRE and CLR are inactive (high), data at the data (D) input … is transferred to the outputs on the positive-going edge of the clock pulse. … Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.