My design is as follows.power supply pin has an 0.1uF bypass capacitor. The 6 channels of the chip are designed the same，Takes channel1 as an example.First pull-down with a resistance which value is 680K, then RC filtering(3K+33pF).All 6 outputs go to FPGA.
Sometimes the output of SN74LVC14A becomes as follow .
I need help.If you can speak Chinese,let me know,thank you .
Hello,
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My design is as follows:power supply pin has an 0.1uF bypass capacitor. The 6 channels of the chip are designed the same，Takes channel1 as an example.First pull-down with a resistance which value is 680K, then RC filtering(3K+33pF).All 6 outputs go to FPGA.
Sometimes the output of SN74LVC14A becomes as follow .
See the following figure for the rising edge
Abnormal time output high level waveform as shown below.It looks like it's oscillating
Chip power consumption has increased dramatically during the problem.
These are the problems I have encountered.
