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CD74HC93: CD74HC93 question

Mickey Zhang
Genius 12080 points
Part Number: CD74HC93

Hi team,

The customer is using CD74HC93. He uses the a 4-bit ripple counter. The Q0 pin is connected to CP1 pin.

The input channel is CP0 pin. VCC is 5V. The schematic is in the attachment. 

Now the customer would like to verify the TRUTH TABLE of the datasheet. According to the TRUTH TABLE, I have drawn the Q0~Q3 waveform. 

Please check the attachment. But I do not know the relationship between the input pulse signal waveform and the Q0~Q3 output waveform.

Would you please send me the input pulse signal waveform? Then I will know the output signal start to reverse in Rising edge or falling edge 

of the input pulse signal. 

What is the frequency range  for the input pulse signal ?

Best Wishes,
Mickey Zhang
Asia Customer Support Center
Texas Instruments

  • 0
    TI__Guru* 96712 points

    Hi Mickey,

    First, I would recommend against placing capacitors at standard CMOS inputs (such as CP1\ and CP0\).  This can cause slow edges which will result in oscillations and erroneous outputs.  If input signal filtering is required, it should be done separately and only a clean/fast edged logic signal should be presented to the CMOS inputs.  If you need help with developing a filter circuit, please give me the requirements and I will be happy to help.

    The maximum guaranteed operating frequency is listed in the datasheet - at 5V you can input 30 MHz at room temperature, 24 MHz from -40C to 85C, and 20 MHz from -55C to 125C.  Higher frequencies may work, but are not explicitly guaranteed, which is why the datasheet shows these as 'minimum' values.

    When the device is first initialized, all outputs will be LOW.  When the first HIGH to LOW transition is detected at the clock input, the output will change states to HIGH and will then follow your drawn waveforms (assuming your circuit is configured properly).  If you change the labels on your drawing, Q0 -> input, Q1 -> Q1, Q2 -> Q1, and Q3 -> Q2, then you will have an accurate set of waveforms.

    The schematic shown above doesn't really tell me anything - you just have the signal lines labelled, so I have no way of knowing what is connected to the device, how the pins are to be connected together, or even if it is driving any load or receiving any signals.  If you would like my help in improving the schematic, I would need to see what is happening at each pin, including what devices are driving them and what devices are being driven by them.

  • 0 in reply to Emrys Maier
    TI__Genius 12080 points

    Hi Emrys,

    Thanks for your reply.

    Q1:　For the customers's schematic, the input is CPO pin. Is this correct?

    Q2: What do you mean by "Q0 -> input, Q1 -> Q1, Q2 -> Q1, and Q3 -> Q2"? Would you explain more about this?

    Q3: You mean the output waveform will change in the falling edge of the input clock?

    Q4: For my drawing waveform, The cycle of Q1=2*the cycle of Q0. The cycle of Q2=2*the cycle of Q1. The cycle of Q3=2*the cycle of Q2.

    I would like to verify if the cycle of Q0 is 2* the input pulse cycle.

  • 0 in reply to Mickey Zhang
    TI__Guru* 96712 points

    Q1: For the customers's schematic, the input is CPO pin. Is this correct?

    The input of this device is at CP0\, however the given schematic is not configured as a 4 bit frequency divider -- CP1\ must be connected to Q0 as indicated in the datasheet. 

    Q2: What do you mean by "Q0 -> input, Q1 -> Q1, Q2 -> Q1, and Q3 -> Q2"? Would you explain more about this?

    Q3: You mean the output waveform will change in the falling edge of the input clock?

    Q4: For my drawing waveform, The cycle of Q1=2*the cycle of Q0. The cycle of Q2=2*the cycle of Q1. The cycle of Q3=2*the cycle of Q2.

    I would like to verify if the cycle of Q0 is 2* the input pulse cycle.

    I believe an image will help to clear this up:

  • 0 in reply to Emrys Maier
    TI__Genius 12080 points

    Hi Emrys,

    Thanks for your help.

    For the customer's schematic, Q0 is connected to CP1. According to your suggestion, remove CQ3 and CQ4, then it will be correct?

    For the above waveform, there is no Q3 waveform. How about the Q3 waveform?

  • 0 in reply to Mickey Zhang
    TI__Guru* 96712 points

    Hello Mickey,

    After removing CQ3 and CQ4 the circuit shown will be correct.

    The waveform for Q3 will be the division of Q2 by 2 - the same that Q2 is the division of Q1 by 2, Q1 is the division of Q0 by 2, and Q0 is the division of the input signal by 2.