Hello support team,
According to the datasheet of the device above, the specification of the power-up ramp rate is 200 μs/V or more.
What happens if the ramp rate is less than 200 μs/V?
1. Large current will flow only during the period when the power supply rises to the specified value.
2. latch up or breakdown will happen.
3. Any other something else will happen.
Best regards,
M. Tachibana
Hello Tachibana-san,
I'm afraid I don't have data on the results of violating the power-on ramp rate, however I can speculate on the reason we have that spec.
Each input on a bus-hold device has a weak latch to maintain the input at a valid logic level. The latch is essentially a feedback circuit, as shown here:
Highlighted in red is the added circuitry to a normal CMOS input to produce the bus-hold latch.
If the supply were slowly ramped, it is possible for the thresholds for these two devices to be different due to process variation and low-voltage operation (below our rated operating voltage). If the thresholds are different, this circuit becomes an oscillator, and will cause excessive current draw.
I believe this to be the reason for the supply ramp rate specification.
To simplify this, we cannot support an application in which the datasheet values are violated - so if this device is being used in a system with a slower ramp rate than 200 μs/V, we cannot guarantee anything about its operation.
