SN74LVC74A: what's minimum time between CLK and /CLR?

Max Han

Intellectual 2260 points

Part Number: SN74LVC74A

Hi,

in customer application, /CLR is behind CLK, but some chips Q output is high, and some Q output is low.

over 8 years ago

0 Max Han over 8 years ago

TI__Intellectual 2260 points

below is customer's circuit, right now, customer increased C971 capacitor, /CLR rising edge is more behind CLK, so Q is normal.

what's minimum time between CLK and /CLR?

thanks.

0 ShreyasRao over 8 years ago in reply to Max Han

TI__Guru 62160 points

Hi Max ,

i believe you are referring to the question in the FAQ :e2e.ti.com/.../3538.03-output-parameters

The initial state of the flip flop during power up is unknown until a valid input has occurred. In this case , the CLR input is asynchronous to the CLK input , meaning the CLR input overrides the CLK and D input and clears the Q output. however, the default power up state is still unknown.

I see that the input clk and clr has very slow rising edge almost 800us for power up which is violating the transition rate requirements. this is because of the 0.1uF cap on the input pins, could you remove it ? Refer to the app note on slow inputs and its effects on outputs. consider using a schmitt trigger to square up the signals. www.ti.com.cn/.../slla364a.pdf
I also notice that the low is not at ground ? am i missing something ?

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SN74LVC74A: what's minimum time between CLK and /CLR?