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TXS0108E-Q1: Input transition rate

Bhavesh Tailor
Intellectual 290 points
Part Number: TXS0108E-Q1
Other Parts Discussed in Thread: SN74LVC1G08

Hi,

In section 6.3 of the TXS0108E-Q1 datasheet there is a specification for input transition rate to be no greater than 10ns/V for Push-Pull I/O's. 

Is there also a transition input rate requirement for Open-Drain I/O's?

Look forward to your response.

Many Thanks,

Bhav

  • 0
    TI__Guru* 97066 points

    Hi Bhav,

    This spec is for any input signal:

    The "Push-pull" in the datasheet is misleading and should be removed - it is referring to the internal structure of our device and has nothing to do with the type of connected external device. This spec is for any type of input, and prevents oscillation and shoot-through currents. You typically only see the "input transition time" spec in CMOS devices due to their input structure.

  • 0 in reply to Emrys Maier
    Intellectual 290 points

    Hi Emrys,

    Thanks for your informative response.

    However, I am a little confuse as this input rate spec translates to a maximum 26.4ns 10-90 input rise time for Port B with VrefB = 3.3V, yet the maximum output rise-time given in section 6.11 for Port A is 508ns.  Wouldn't the one-shot accelerator produce a faster output rise than the input?

    The circuit I am testing that is using this translator is used to translate I2C signals between 1.8V and 3.3V.  I get the following input rise-times for the SDA line:

    Port A (1.8V) = 74ns

    Port B (3.3V) = 65ns

    Are these input rise times acceptable?

    Look forward to your response.

    Many Thanks,

    Bhav

  • 0 in reply to Bhavesh Tailor
    TI__Guru* 97066 points
    Hi Bhav,
    I will have to check with our resident expert on this device, but I think the "Open-Drain A-port rise time" you referenced seems really slow because of how the measurement is defined. If you look in Figure 10, you can see the difference in how an open-drain input is compared to a push-pull -- essentially, the input voltage edge is being defined at VCCI*0.2, which is long before the one-shot is actually being triggered, which results in a long 'rise time' on the output. This is the only way I could think of that the output edge would appear so slow... the input edge really shouldn't affect the output except in some extreme circumstances.

    You input rise times are likely fine, but they technically don't meet the datasheet spec. A 10 ns/V input edge rate is very standard for most CMOS inputs (Example: SN74LVC1G08). How are you testing the edge rates? I wonder if there isn't some stray capacitance added by the probe that is making them appear slower than they are.