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LSF0108: What's the leakage current of I/O pin

Part Number: LSF0108

Dear Team,

What's the leakage current of each I/O pin?

As I understanding, the internal structure of LSF is MOSFET with driver and some logic.

When the input high, the inter MOSFET been turn off. With pull high voltage, there should be a leakage path for high impedance node.

Thanks 

Shaq

  • Hi Chen,

    The IO ports of LSF are not high impedance CMOS inputs like the other devices (Direction controlled or unidirectional).
    You are right about the internal structure of LSF which has NFET. The control is derived from the external biasing of the 200k resistor and the supplies which sets the gate voltage at the IO ports.
    During input low, the FET is switched on and connects the input to output node through low impedance path.
    During input high, the FET is switched off, output is pulled by the external resistor.
    The leakage paths will be to ground through the input/output negative clamp diodes, and through the switch from input to output.
    Assuming 1Mohm resistance during switch off the case, the leakage will be ~5uA similiar to the Enable pin specification given on the datasheet.