I'm using the SN74LV594A (8 bit shift register with separate shift and storage registers) in a design that will be driving a bunch of other logic devices including FPGAs. Naturally, some of these devices generally do not like floating inputs. They must be driven either high or low continuously from power-up. The 594A has a storage register that appears to continuously drive the 8 outputs of the device, i.e. there is no output enable or therefore any risk of the outputs going highZ and hence the inputs of the other devices floating...so I believe I'm in good shape and shouldn't have to provide explicit pull ups / downs.
However, I am curious about the default / power up state of the output and whether there is any period of time when the outputs are not driven. There is no information about this in the datasheet.
Can anyone clarify this for me?
