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SN74LV06A: Output behavior during power off

Part Number: SN74LV06A

Dear Technical Support Team,

When A ports(input) are LOW during power off, Hi impedance(output)  are guaranteed from VCC=3.3V to 0V? 

Behavior during power off is shown following figure, however I couldn't find power-off.

SN74LV06A supports Ioff.

Best Regards,


  • Hello ttd,

    Ioff (Partial Power Down Mode and Back Drive Protection) is specified at Vcc = 0 V only.  If your supply is at 0 V, then the output is guaranteed to be in a high-impedance state with leakage as specified by Ioff (5 μA max for this device).

    The above plot shows the device's expected output when the supply is ramped from 0 to 3.3V and the output is pulled-up to the same supply.  Note that the device cannot drive the output low until ~1V, which is approximately when the internal FETs have enough field bias to operate correctly.

  • Hi Emrys Maier,

    Thank you for your reply.

    Datasheet Page.1 shows below.

    "Outputs are Disabled During Power Up and Power Down With Inputs Tied to VCC "

    Does it guarantee Hi-z on power up or power down until valid internal logic?  

    Best Regards,


  • This plot is only typical behavior (ie not guaranteed across all possible conditions). The device is only guaranteed to be in high impedance at Vcc = 0V and to operate correctly from 2V to 5.5V, as per the recommended operating conditions table.