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SN74LVC8T245: could support 75Mhz when 3.3V to 1.8V

Rory Wu
Intellectual 1050 points

Part Number: SN74LVC8T245
Other Parts Discussed in Thread: SN74AXC8T245, SN74LVC2T45

Hello, my customer used SN74LVC8T245 in their BT656 protocol level shift from 3.3V to 1.8V, but the date will be lost. Please refer to the waveform of the CLK and data.

The frequency are 74Mhz and 37Mhz as measured.The amplitude of CLK will not as high as 1.8V. I am not sure if this device could support 74Mhz from 3.3V to 1.8V. I could only found tp data in the D/S. Could you help share tr data for the rising and falling time? Please also help check the waveform as attached, thanks!

CLK CH1-output CH2-input

D7_CH1-output CH2-input

  • 0
    TI__Guru 64030 points
    Hi Rory,

    Is there a schematic associated with this?
    I would like to know the loading(current loading and capacitive loading) at the IO ports. the point at which this is being measured.
    what is the probe capacitance?
    There should not be a problem with the device supporting 75Mhz but it rise time/ fall time / prop delay all depends on the cap loading at the output.
  • 0 in reply to ShreyasRao
    TI__Guru 64030 points
    Hi Rory,

    For 3.3V to 1.8V down translation, would you consider switching over to our newly released SN74AXC8T245 device which can support such high data rate?
    LVC is not optimized to operate at 1.8V but the AXC and the AVC8T245 are optimized for lower operating voltages.
    Both AXC and AVC are P2P to LVC device.
    www.ti.com/.../SN74AXC8T245EVM

    There is also an EVM for the AXC8T245 which can be ordered and tested.
  • 0 in reply to ShreyasRao
    TI__Intellectual 1050 points

    HI Shreyas,

    This is tested without load. if adding load, the amplitude will be less.

    Could you help check the rise time/fall time in no load condition?

    CLK:

    D7:

  • 0 in reply to ShreyasRao
    TI__Intellectual 1050 points
    Hi Shreyas,

    This project is ready to MP in customer side. So they may have not enough time to evaluate a new device. You said there should not be a problem with the device supporting 75Mhz. Could you please help confirm the signal I send you? Does rise time/ fall time match to our device? Thanks!
  • 0 in reply to Rory Wu
    TI__Guru 64030 points
    Hi Rory

    The CLK signal seem to be heavily loaded and hence the amplitude is less as compared to D7 signal. It seems that the CLk signal is being fanned out to other devices as well which could cause this.
    Is this causing the receiver side to fail ( not recognize as high signal)?
    I couldnt find the data rate support mentioned in the SN74LVC8T245 datasheet, however, i looked into SN74LVC2T45 device and it mentions 75Mbps for 1.8V translation which is ~37Mhz.
    The AXC or the AVC supports higher datarates (170Mbps as per datasheet)
    As I mentioned here, the LVC is not optimized(doesn't have enough drive strength, maintaining rise/fall time to support high speeds) at low voltage.
  • 0 in reply to ShreyasRao
    TI__Intellectual 1050 points
    Hi Shreyas,

    CLK is 74Mhz and D7 signal is 37Mhz. So I think that is why you said it seem to be heavily loaded. Do you mean that the highest speed LVC part could support is 37Mhz?
  • 0 in reply to Rory Wu
    TI__Guru 64030 points
    Hi Rory,

    The highest speed LVC could support at 1.8V drive voltage is ~38Mhz.
    It can support higher data rate at 3.3V or beyond (higher drive strength at the higher voltage)
  • 0 in reply to ShreyasRao
    TI__Intellectual 1050 points
    Shreya,

    Got. Thanks!

    BR,
    Rory