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SN74LVC1G17: Noisy output behavior - screen shots included

Robbie Valentine86
Expert 1550 points
Part Number: SN74LVC1G17
Other Parts Discussed in Thread: SN74AUC1G17

Hello,

I'm using this part to receive a trigger that could have a slow rise time.  The intention is to use this part to provide clean rising and falling edges to the next IC in line.  I have a few questions though.

ch1. is the input

ch2. is the output

1.  Where do you find the rise/fall times (slew rate?) in this data sheet?  It doesn't seem to be listed.

2.  I'm testing with this part now and the below screenshots of operation with a 1Mhz square wave input (3.3Vpp with Vcc = 3.3V) from a TEK sig gen raise some questions.

a. Why is the output so noisy?

b. The rise time seems to be ~10nS.  Does this make sense?  I'm trying to reconcile this with the data sheet.

3. Why does section 10.2 reference a (delta t)/(delta V)?   I cannot find this in the datasheet.

Note about schematics:  The part is implemented on a PCB with NO decoupling cap (this could be contributing to the noise seen in Ch2 (red)??).  There is no output cap and no input cap on the input/output pins.  This part is driving a clock input of another IC that does not list a spec for this pin's input capacitance.  

fig1

fig2

  • 0
    TI__Guru* 97046 points

    Hi Robbie,

    Thanks for the detailed post.

    I'll address each question individually, but first I should mention that if you want to get the absolute fastest edges when running at 1.8V, try an SN74AUC1G17. Those are really optimized for 1.8V operation at high speed. The LVC family is more optimized for 3.3V operation.

    1.  Where do you find the rise/fall times (slew rate?) in this data sheet?  It doesn't seem to be listed.

    The datasheet does not have output edge rate data (nor does any logic datasheet). The closest thing you will find is output drive strength (VOH/VOL and IOH/IOL) which can be used to estimate output impedance.

    2.  I'm testing with this part now and the below screenshots of operation with a 1Mhz square wave input (3.3Vpp with Vcc = 3.3V) from a TEK sig gen raise some questions.

    Can you describe your test setup? Or better yet, post a schematic of how it's setup?

    I know you say the Vcc is 3.3V here, but I see a 1.8V signal on the scope shots (pink signal is set it 1V/div and it's about 2 divisions high). If the supply were at 3.3V, you'd probably see much better edges from the LVC device.

    a. Why is the output so noisy?

    Without a lot of details, I couldn't really say.

    b. The rise time seems to be ~10nS.  Does this make sense?  I'm trying to reconcile this with the data sheet.

    Yes, 10ns isn't so bad for a 1.8V supply at ~30pF load.

    3. Why does section 10.2 reference a (delta t)/(delta V)?   I cannot find this in the datasheet.

    It's an error in the datsheet. The dt/dv spec is intended for non-Schmitt-Trigger input devices, and was probably copied there by mistake when the datasheet was updated to have an "Applications" section.

    Note about schematics:  The part is implemented on a PCB with NO decoupling cap (this could be contributing to the noise seen in Ch2 (red)??).  There is no output cap and no input cap on the input/output pins.  This part is driving a clock input of another IC that does not list a spec for this pin's input capacitance.  

    That can definitely add noise.

  • 0 in reply to Emrys Maier
    Expert 1550 points
    I apologize - you are correct - this part is indeed powered from 1.8V. I will try to get you the schematics very soon. I guess i'm not really out of the ball park in general though with a 5 to 10nS rise time for this part.
  • 0 in reply to Robbie Valentine86
    Expert 1550 points

    Here is the schematic originally.

    The input trigger comes from a 50 ohm transmission line so that is why the 50 ohm termination is there.  R1 has been changed to a 0R.  I added a .1uF ad .01uF decoupling cap to pin 5.  The output drives the input to a clock fanout buffer. I don't know the capacitance on that pin though.