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SN74LVC2G74: Transition times / using CLR, PRE inputs

David D
Intellectual 580 points
Part Number: SN74LVC2G74

Hi,

In section 6.3 - Recommended operating conditions, you specify that for Vcc=5V the "Input transition rise or fall time" should be dt/dV=5nS/V (MAX).

Meaning that slow transition might be problematic.

Which inputs does this specification refers to?
I'm asking cause later in the doc, you use an RC circuit on the CLR input presumably to set the output to a known value after the power up.

(At least this is what I intend to do with this input).

But such a circuit will likely violate the transition time spec.

Please elaborate.

  • 0
    TI__Guru* 97046 points

    Hey David,

    Good catch.  The RC circuit there will definitely violate the input edge rate on the CLR\ pin. That application wouldn't make it past our engineering team today, but it seems to have slipped through in years past.

    The fact is though, many many engineers have used CLR\ initialization circuits like this for years without having problems.  The primary concern with slow edges is that you can get oscillation and excessive current on that input during the transition. Since this edge only happens once each time the system is powered, and clearing the device more than once during startup isn't really a problem, this configuration typically isn't a problem.  The primary concern would be with reliability due to the added current during power-on.

    The best fix for this is to add a Schmitt-trigger buffer, as shown in this video:

    Eliminate Slow or Noisy Input Signals