Hi all,
We use the PCI2050 bridge with 4 subscribers on the PCI_L1 bus and 5 subscribers on the PCI_L2 bus.
On the PCI_L1 bus our master is a FPGA and the Bridge is a target.
On the PCI_L2 bus our master is the Bridge with 5 targets.
1/ Is it possible to use the PCI_L1 clock for the PCI_L2 bus targets ? (as consequence we don't use the S_CLKOUT of the Bridge to synchronize the PCI_L2 bus.)
2/ Do this design can create some risks with the signal sampling of PCI_L2 bus by the Bridge?
3/ Do the bridge samples signal on its secondary interface according to its primary clock input (P_CLK) or according to its secondary clock input (S_CLK) or according to its secondary clock output (S_CLKOUT) ? (we have some doubts with our interpretation of the datasheet)
Thanks very much for your assistance.
Sincerely,
Seb
