SN7497: Frequency Multiplier.

The SN7497, while being called a frequency multiplier, is actually a frequency divider, as it multiplies the input frequency with n (=0-63) and divides it by 64. So the output frequency goes from 0 to f*63/64 Hz (the multiplication factor is <1) and is never higher and not even equal to the input frequency.

For raising a frequency, there are several mechanisms available. The most common (but also most energy hungry) is using a PLL (phase-locked loop) which can synchronize a self-created high frequency with a base input frequency by adjusting the output frequency by its phase in relation to the input clock edges (simplified explanation).  As a result, virtually any output frequency( or rather virtually any (even non-integer) factor between input and output) can be achieved.

A second, less precise aproach ist the frequency locked loop. Here is a generated output frequency compared to the input frequency by comapring the number of ticks of both frequencies. (e.g. numbber of output tickes during n input ticks). The actual relation between the two is compared to the configured (integer) factor and the output frequency generator is adjusted (usually in discrete steps) in one or other direction.

The AVERAGE output frequency over a certain time is the an integral multiple of the input frequency.

For exactly doubling the input there are two ways:

first, generate a sinusodial wave from the input clock. Then rectify it. You'll have a rectified sinusodual signal which can be turnedinto a rectangular signal by a gate with schmitt trigger input. The frequency is excatly double the input but it you'll have a phase shift between the common edges and the duty cycle (based on the schmitt trigger input characteristics and the pseudo-sinusodial generation) won't be 50%. This can maybe manually adjusted to come near. And the phase shift can be corrected by synchronizing the rising edge of the output signal with the rising or falling edge of the input signal.

if the input frequency is known, you can use a monoflop with an output hold time of 25% of the input frequency and trigger it with the rising and falling edge of the input signal. So the output clock will be synchronized wiht the input signal edges and the duty cyle depeds on the input duty cycle and the exact time constant iof the monoflop.

The easiest way, however, is using a 400kHz crystal oscillator (or a binary multiple of 400kHtz and a divider) and syncronize it with your 200kHz signal. There are some which allow synchronization. Or you use the reference clock signal to reset a divider fed by a clock signal that is a multiple of your desired 400kHz. E.g. use a 4MHz crystal oscillator and a decimal counter, reset it with your 200kHz falling edge (edge-triggered reset!) and use the /10 output signal. The maximum phase shift is then 5%, the duty cycle is 45-55%

The voltage level of the output dpends on the output characteristics of the used parts. You can adjust it by e.g. powering an AND gate (CMOS technology!) with the desired output voltage and feed the signal into the input. (as long as the input signal is then still in the allowed range for the CMOS chip and the output load doesn't cause a voltage drop)

In most cases, however, the exact voltage is unimportant as long as it is in the proper range (5V, 3.3V etc.) for the following circuitry.

Hi Muhammad,

as Emrys said, it's your job to design your circuitry. Whether it is a homework from studies or an engineers job - you won't learn anything if you ask for a ready-made answer and can't cope with possible problems when you don't understand it.

However,
a simple google search for 'frequency doubling ic' revealed quite some solutions. The very first one, www.maximintegrated.com/.../3327 is a really smart solution, along the lines of my proposed monoflop approach. The resistor and capacitor at the inverting input roughly configure the output frequency (15MHz in the example, so you'll need to increase the RC time constant by roughtly a factor of 50) while the two resistors at the non-invertign input adjust the output duty cycle.
note that the shown circuit uses a VHC (very high speed CMOS) gate and a very fast comparator but for your low frequency, a normal HC gate and a slower comparator would be sufficient.

The same google search finds loads of circuitry pictures for alternative aproaches too.