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SN74LVC1G123: Minimum retrigger time Rext value

Dan Andersen
Genius 11460 points
Part Number: SN74LVC1G123


My customer is using the SN74LVC1G123DCUR to provide a high level output as long as the input is above a certain frequency.  Figure 7 of the datasheet gives the minimum retrigger time, which would indicate the minimum frequency required for a given Cext (and supply voltage) to provide this function - but I don't see a mention of Rext in this curve (which would also have an effect on this).  What is the Rext value for this curve?

In my customer's testing with an Rext=10k and Cext=0.01uF (supply=3.3V) they see a constant output when the input frequency is >10kHz...

Thanks,

Dan

  • 0
    TI__Guru* 97066 points
    Hey Dan,
    It's important to note that a one-shot like SN74LVC1G123 will have significant variance in the output pulse width. How accurately are they trying to detect <10 kHz? If the SN74LVC1G123 is setup to generate a 100us pulse, assuming you have the most accurate capacitor and resistor on earth, I would expect to see up to 10% variance from our device (typical 5% over temp), which means you'd have to get below 9.09 kHz for the device to indicate there's a problem -- in the worst case.

    Have they considered using a PLL and phase matching to a generated clock? The output phase difference could be used similarly to indicate a failure of the clock input. This solution would be pretty power hungry.
  • 0 in reply to Emrys Maier
    TI__Genius 11460 points

    They just want the output high if the input is above a certain frequency.  In their testing they have been able to achieve this at >10kHz with Rext=10k and Cext=0.01uF, but they were expecting a much higher frequency required given Figure 7, so they wanted to make sure they understood it correctly.  To me, it appears Figure 7 is missing some critical circuit condition, namely the value of Rext.  Do we have more info on the circuit conditions for Figure 7 - or am I missing something - or both! ;)

    Using a PLL is also a good idea that I will mention to them.

    Thanks,

    Dan

  • 0 in reply to Dan Andersen
    TI__Guru* 97066 points
    Hey Dan,
    The minimum retrigger time is only reliant on the capacitor because the resistor is essentially bypassed when the device is forcing a discharge or charge of the external capacitor.
  • 0 in reply to Emrys Maier
    TI__Genius 11460 points
    That makes sense! So then they just need an output pulse width set longer than the retrigger time - and an input pulse happening faster than that - for the output to remain high continuously for a given input frequency. I think I've got it now. I appreciate the support!