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SN74LVC1G17: Single Schmitt-Trigger Buffer: Input Rise time and fall time specs missing in data sheet

Daniel Ka
Intellectual 607 points
Part Number: SN74LVC1G17

Hi there, 

from the Application Report "Implications of Slow or Floating CMOS Inputs" (SCBA004D) I learned that slow input signal edge rates or transition times can be of concern.

I've read some 74HCT* datasheets and these devices seem to have typical have input signal transition times of about 500ns when operating at about 5 V.

Whereas logic elements based on very advanced high speed CMOS technology (e.g. 74LVC family) have much stricter input signal requirements, i.e., specifying input edge rates of max. 10 ns/V.

Now the SN74LVC1G17 datasheet does not state rise time and fall time specs for the input signal (although in section 10.2.2 they are referenced).

Why is this? Has it been omitted in error? Is this because the buffer is a schmitt trigger based design with input hysteresis? Or should I rather assume the "average" input transition rate for the 74LVC family of max. 10ns/V.

An while we are on it, does a similar restriction exist for bipolar based logic elements, e.g. 74LS...?

Thanks!

Daniel

  • 0
    TI__Guru* 97046 points

    Hello Daniel,

    The SN74LVC1G17 is a Schmitt-trigger buffer, meaning that it has Schmitt-trigger inputs.

    The application report Understanding Schmitt Triggers includes a great deal of information about these devices, but the intro says it all:

    Bipolar devices do _not_ have the same restriction. They operate very differently... however you will find that CMOS is superior in almost every way. If you want to prevent excessive supply current by switching to a BJT based device, you will find that the static current of those devices is typically measured in mA, while CMOS device are measured in uA or even nA.

  • 0 in reply to Emrys Maier
    Intellectual 607 points
    Thanks Emrys for the prompt and helpful response!

    I believe the important statement of the document you quoted is "A true Schmitt trigger input will not have rise and fall time limitations". It's a pitty that this important piece of information is missing from the document "Implications of Slow or Floating CMOS Inputs" www.ti.com/.../scba004d.pdf

    Anyway, great news.

    I conclude that this means that SN74LVC1G17 (Single Schmitt-Trigger Buffer) can handle slow "edged" input signals and convert them into signals with a much faster transition rate. Consequently, it generates a signal that is suitable as input signal for subsequent 74LVC* logic elements that do not include a Schmitt trigger input.

    Thanks again!
    Daniel