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SN74AVC4T245-Q1: Output State During Power-Up

Jordan White
Prodigy 20 points
Part Number: SN74AVC4T245-Q1
Other Parts Discussed in Thread: SN74AVC4T245

The datasheet for the SN74AVC4T245-Q1 (page 19) states that to ensure the high-impedance state of the outputs during power up or down, the OE pin must be pulled high.

I DO NOT need to guarantee the outputs are high-impedance during power up, but I DO need to guarantee they will NOT be driven high.

For example, if the initial condition is:

* VCCA, 1DIR, and 2DIR are all stable at 3.3V

* 1OE, 2OE are tied to ground

* 1A1, 1A2, 2A1, 2A2 are all pulled low

* VCCB pulled low (VCCB un-powered and pulled low through a resistor)

If I then apply power to VCCB, I need to ensure the outputs will not be driven high at any point as VCCB ramps up.

Can you please comment on expected operation in this scenario?

  • 0
    TI__Guru 61940 points

    Hi Jordan,

    Welcome to e2e.

    In your case, the expected output behavior of the SN74AVC4T245 B ports would be to stay low since all the inputs are actively held low.

    do you have schematic and scope shots if already conducted experiments on the device? I am wondering if the pulldown resistor on the Vccb supply would cause higher current leakage during normal operation.

  • 0 in reply to ShreyasRao
    Prodigy 20 points
    Shreyas,

    Thank you for the response. I do not have oscope plots currently as I am still in the design stage. I just needed to ensure the outputs of the device would be known given the pwr / input scenario I described.

    Thank you again for your response.