SN74LVC1G74DCUR - Trying to use this as a frequency divider

Thank you for the reply!

The ground is well connected to pin 4 and 4.919V are present at pin 8. A strong, 4.8V clock with a 30 ns rise time is present at pin 1.

Pins 2 & 3 are connected by a solder bridge that has sub-ohm resistance.

Acceptable digital signals are present at pins 3 & 5 with pin 3 being in phase with the clock and pin 5 being 180 deg out of phase with the clock. Both pins are phase locked to the clock and are operating at the same frequency as the clock. There is no edge oscillation at either the input or the outputs.

Out of desperation, I replaced the chip and have the same results.

Thanks

Hi Jerry,

Can you provide a picture of your setup and oscope shots of the input/output signals?

First thing Monday.

Thanks!

Jerry

Channel 1 (YELLOW) = clock

Channel 2 (BLUE) = PIN 3

Channel 4 (GREEN) = PIN 5 (NOTE - 5V/cm)

 

Thank you.

 

Jerry

Zoom in on the rising edge - I'd like to see the timing and at the μs scale I can't tell what's going on.

Also - can you provide a pic of the test circuit?

Pins 2 & 3 are shorted

Hey Jerry,
Thanks for the layout and scope shot. I was hoping to get a picture of the device so I can check the topside markings against our lot trace codes.

Also, can you get a shot of the falling edge with the same time scale (50 ns)? It's certainly very odd that the device appears to be triggering on the falling edge....

Hi Emrys,

Sorry it took so long. I had an accident and had to replace the 5V regulator. A picture of the package, rising and falling edge data is attached.

I'll look up that LTC tomorrow when I get in to work.

In the mean time, can you try adding a 0.1uF bypass capacitor between pins 4(GND) and 8(Vcc)?

Hey Jerry,
I was able to verify that those are legitimate TI parts.

I'm going to order some samples and try to replicate your issue here. It will take a couple days.

Emrys,

Thank you. I installed a 1uF cap directly across the chip with leads as short as possible. The cap was already bypassed with a 0.01uF directly under the chip but I did not have a suitable surface mount replacement.

Now it gets weird. If I measure with a single probe at either pin 3 or pin 5 there is no apparent change in behavior from yesterday. But when I measure both pins simultaneously, I get frequency division but there is a huge glitch in the middle of the high signal corresponding to a rising or falling edge. Rising or falling depends on if I am looking at Q or Qbar.  I am using standard Tek X10 probes, 10 Mohm, 10 pF. Is this introducing some small phase shift?  I have attached an image of the downstream circuit. Given what that circuit is, I am at a loss to explain how the scope probes are doing what they are doing.

When you've been measuring signals, are they at the pins of the device, at the source, or at test points? If you can, get signals directly at the pins. The ones I'm most interested in are the clock and D and Q\ pins.

Emrys,

Thank you. I installed a 1uF cap directly across the chip with leads as short as possible. The cap was already bypassed with a 0.01uF directly under the chip but I did not have a suitable surface mount replacement.

Now it gets weird. If I measure with a single probe at either pin 3 or pin 5 there is no apparent change in behavior from yesterday. But when I measure both pins simultaneously, I get frequency division but there is a huge glitch in the middle of the high signal corresponding to a rising or falling edge. Rising or falling depends on if I am looking at Q or Qbar.  I am using standard Tek X10 probes, 10 Mohm, 10 pF. Is this introducing some small phase shift?  I have attached an image of the downstream circuit. Given what that circuit is, I am at a loss to explain how the scope probes are doing what they are doing.

Sorry about the re-post. I will get the data tomorrow.

Hey Jerry,
Just to let you in on what I'm thinking:

There's probably a timing issue going on.

The device requires a small amount of setup time (before clock edge) and hold time (after clock edge) for the data input.

From your original scope shots, I assumed these were both being met -- which led me to believe the parts weren't genuine TI -- ie they were misbehaving because of bad design.

However, if the data wasn't taken at the pins of the device, it's possible that things are not as they appear. If there is excessive capacitance on the clock or data line, the signal could be delayed, resulting in one of those required timings not being met.

The frequency divider circuit is pretty sensitive -- since it uses internal feedback, it really counts on the timing of everything to be perfect.

Hopefully your new scope shots will show us something helpful. Either way, I have ordered parts so I can do some testing on my end.

Hi Emrys, 

First, let me start by saying thank you. I really appreciate the time and effort that you have put into this.

So, my results are very similar. Depending on which probe I use, I can actually get an eye pattern.  The chip is blazing fast.  So here is the question: can I use an RC on the D line to slow things down or should I abandon the approach and "dead bug" a JK onto the board? Unfortunately, the production boards are already built.

Again, thank you so much for your time.

Jerry

Hi Emrys. I apologize as I didn't fully read the email. I will install the caps and let you know how it turns out.

Thanks!!

Jerry

Hi Emrys,

I tried 15 and 33 pF.  The output looks a bit more stable but there is no frequency division.

Any other ideas?

Thanks

Jerry

Hey Jerry,
I'm afraid that I'm out of ideas.

Were you ever able to get scope shots directly at the device pins?

Hi Evan,

If the circuit is this sensitive and unpredictable, I don't think it is worth any more of a fight. I am going to dead-bug a JK rigged as a T and move on.

Thank you so much for digging into this. I really appreciate it.

Jerry