SN74LVC8T245: IBIS model issue

Hi Karan,

Actually we are using this buffer for 1.8V(A-port) to 3.3V(B-Port) translation. Each output from port-B connected to four different devices(Multi-point) as like below.

This signal Max toggling rate will be 50Mhz.  

Input capacitance can be considered same as this buffer.

We want to know, signal quality on all receiver side.

Can you suggest us how we can validate this configuration??

Hi Ramesh,

The IBIS model is one way to know what the output will look like.

Another method is the following SPICE model. The SPICE model is not as accurate however.

I have attached a TINA-TI Spice model for you to test this out. This is a 1 bit buffer and I have set up a test bench for you. If you run a transient analysis it will give you what the output looks like. You can change the load to represent all line capacitance and load you might have from what you are driving.
SN74LVC.cir

SN74LVC_Behavioral_Model_v180615.TSC

Thanks!

- Karan

Hi Ramesh,

There appears to be an extra character at the end of the file. This sometimes happens when we upload a file. We've not identified what causes this, but you can delete the character after [end] with any text editor and HyperLynx should load it without a problem.

David