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SN74AVC4T774: Questions

Go Bravos
Expert 6090 points
Part Number: SN74AVC4T774

Team,

1)      If I power the B side of the level translator and the A Side is unpowered and I have a pull up to VCCA on the OE_N line and the direction lines are tied to either GND or VCC A.

  1. When the A Side power rail is ramped up will direction or data lines glitch? (Considering B Side is powered and A Side is ramping up)
  2. While the OE_N is high do both sides of the part need to have pull downs to provide a low or high on the IO lines? (Including the IOs which will be outputs)
  3. Is there any higher current on ICCA or ICCB in these states?

 

2)      If I power the A Side of the level translator and the B Side is unpowered and I have a pull up to VCCA on the OE_N line and the direction lines are tied to either GND or VCC A.

  1. When the B Side power rail is ramped up will there be any data line or direction glitches?
  2. While the OE_N is high does the lines which would be normally outputs required biasing resistors?
  3. Is there an higher current on ICCA or ICCB in these states?

  • 0
    TI__Guru* 97046 points
    Hi Go,
    I have asked our translation expert to look into this. He will get back with you tomorrow when we are in the office.
  • 0
    TI__Guru 62080 points
    Hi Go,

    I encourage having weak pulldown on the devices IO data lines. The reason is that the input circuitry of the device is always active and should have defined states. When the Vcca is powered down, the IO lines are in Hi-Z. The B ports have active input circuitry(irrespective of DIR pin status).
    A weak pulldown using 100k/1M resistors would work. What is the status of the DIR pins while Vcca ramps up?
    1a) Ramping up Vcca with weak pulldown resistors on both IO ports would also ensure no glitches on the DIR or data pins.
    1b)OE high ensures hi-z on IO ports. having defined states on the IO lines when supply is powered would be advised.
    1c) the datasheet specs the Icca and Iccb current and need to pay attention to the test condition where the output has no load and input is at either one of the rails.

    2a) No defined power sequencing for the device, and can be ramped in any order without affecting the reliability of the device. System requirements must be taken into consideration while doing this. no glitches on the IO or data ports when either sides have weak pd resistors.
    2b) i would advise to have it.
    2c) refer to datasheet specs / or 1c.

    Please let me know the application and the requirements for using the AVC4t774. Would customer consider using the newly released AXC family of devices?