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CD4013B: CB4013B

Siddharth Sangam
Intellectual 640 points
Part Number: CD4013B

I am using CD4013B D-FF for Latching purpose.

Here Clock is fixed to Vcc and D input also fixed.

1: Need to know the valid status of Q when Both SET and RESET are low and (Data and Clock are Don't care).This state is not mentioned in datasheet.

2: Do you have any alternative for CD4013 D-Flip Flop with same function table but with higher output driving current and AEC Qualified.

Here it is only 360Ua. Needs current rating around 10mA.

3:Also require its Junction temperature(Not mentioned in Datasheet)

4:Please can you provide me the PSpice model for CD4013B D-FF.

   As per simulation it is showing 0.5*Vcc or half of Vcc.

5:If possible please provide me the application note for the same.

with regards,

Siddharth Sangam

  • 0
    TI__Guru* 96712 points

    Hi Siddharth,

    I will address each question individually to be clear:

    (1) You said the clock is "don't care" (X) -- but that can't be true since the clock rising edge causes a change in Q -- I assume you mean "when the clock isn't being asserted." The output of a flip-flop (any flip-flop) will be the previous state (called Q0) when the SET and RESET pins are deasserted (in this case, LOW inputs) and the clock is not being asserted (in this case, a rising edge).    I'm guessing what you really want to know is the initial state of the flip-flop's output when power is applied.  This is a much more difficult thing to answer, since by definition, no one can know. A latch circuit is inherently unstable at power-on, and will latch into one of two states (HIGH or LOW).

    There's an FAQ on this topic here:

     

    And Google has some interesting reading on the topic as well.

    (2) Unfortunately the CD4000 family of logic is unique in it's voltage range. We do not have any other 18V capable logic devices. You would need to add an external driver to increase drive strength.

    (3)  

    (4) Unfortunately, there is no model for the CD4013B. We are currently working to develop behavioral PSpice models for our older parts (like this one), but it will probably be another year before we get to this device in particular.

    (5) There isn't really an application report on how to use a D Flip-Flop.  Do you have a particular question besides the ones above? I can try to help if I know what you're trying to do.  Maybe you can explain your application a bit?