Other Parts Discussed in Thread: SN74AXC1T45, SN74AXC8T245
Hi,
We would like to level translate 3.3V 125MHz LVCMOS clock signal to 2.5V level.
I have tried looking into logic device datasheets to identify suitable device to support 125MHz level translation with good signal integrity (i.e. minimal distortion in signal) and remove the jitter.
But unfortunately, the information regarding operating frequency is not available in datasheets. All of the parameters seems provided for low frequencies so am I missing to look any data which gives idea about bandwidth of Logic device.
How can I determine if the SN74AUP1T17 work for 125MHz level translation or not?
This is reference clock for RGMII interface so propogation delay is not important but TpHL and TpLH value should be near so duty cycle remain nearly same as input.
Regards,
Bipin