Hey Rod,
Thanks for clarifying. I'll try to help out line by line.
* Input high voltage: 7V-minimum
The minimum input high voltage doesn't indicate when the reset pulse activates - it tells you what your HIGH voltage needs to be at a minimum for the device to work. The actual trigger point is closer to V_DD/2 (5V for a 10V supply).
* RESET pulse width: 30nsec-typical (though confusingly this is also shown as 60nsec-minimum under Recommended Operating Conditions)
As the name implies, we recommend a minimum pulse width of 60ns to reset the device. The actual typical pulse length required for the device to "see" the reset pulse correctly is 30ns. It's highly recommended to operate the device using the values listed int he Recommended Operating Conditions table to prevent any problems.
* RESET propagation delay: 80nsec-typical
This is the time it takes from the time you pull the RESET line HIGH to the time that all outputs have been reset -- ie 50% of the rising RESET edge to 50% of the falling output edge.
* Output Transition (HL or LH) time: 50nsec-typical
This is the time it takes for the output to switch from 10% to 90% (or 90% to 10%) with the given load conditions.
* My understanding/question is the RESET pin does nothing until it sees 7 volts. Then if the 7 volts lasts for 30nsec the Reset input does its thing including sending instructions to other registers. Following (???) the 30nsec "setup time" the RESET signal arrives at the other registers 80nsec later. When it arrives at a HI output pin it takes 50nsec for that output to go LO. This is the complete RESET operation.
The RESET pin is asynchronous logic, meaning that it will immediately start a cascade of changing internal logic gates when the input switches inside the device (at the threshold voltage, ie V_DD/2) to reset all channels. In order for this logic signals to propagate completely, the device must be held in RESET long enough for all registers to receive the RESET signal internally. This typically takes 30ns, and we recommend holding it for 60ns to be certain. Most users hold it for much longer because there's really no need to do this as fast as possible in most systems.
As I mentioned above, the time it takes from the start of the RESET pulse to the outputs changing is the RESET propagation delay. Ie it takes ~80ns for the outputs to get to 50%*V_DD from the time the input crossed 50%*V_DD.
* My question is if the 30nsec RESET pulse width time is coincident with the 80nsec propagation time, or serially sequential? If sequential, does the RESET operation continue if the RESET input goes low after, say, 40nsec? (My circuit won't do that, but I'm curious.)
I hope I've already covered this above clearly enough, but to be as clear as possible, the propagation delay starts at exactly the same time as the RESET pulse width measurement - 50% of the rising edge of the RESET pulse.
Since this datasheet doesn't include the timing waveforms, I figure it's helpful to also post those here:
This figure shows how the propagation delay is measured, from 50% of the input to 50% of the output.
This figure shows how pulse width is measured, from 50% of the input first edge to 50% of the input following edge.
This figure shows how transition times are measured, from 10% to 90% of an edge (or 90% to 10%).
