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SN74LVC2G74: D-FF SN74LVC2G74DCTR Clock operation

Shlomi Yehezkia
Mastermind 6150 points

Part Number: SN74LVC2G74

Hi Team,

On the D-FF I have the clock works opposite than it should.

The Q output changes as clock goes down and not up as mentioned on the DS.

Can you please advise why?

Thanks,

Shlomi


SN74LVC2G74DCTR.docx

 

 

  • 0
    TI__Guru 64030 points
    Shlomi,

    Interesting. This device is positive edge triggered flip flop, which means that the state shouldn't change with the negative edge of the clock as you have mentioned.
    What is the probe setting on the channel 3? Is it somehow set to inverting?
    Also, I do have some general concerns here.
    The Clock is at 2.5V, whereas the output and the D is at 5V? I would advise to not have this mid-level for the clock since the Q is not guaranteed to trigger. The Vih is 0.7Vcc, so Clock must be at least 3.5V for device to recognize as high.
    The rising edge is really slow. with the time scale of 200ms/div, I think this is >~10ms which is also violating the recommended conditions of 5ns/V.
    Have you changed any other device, it would be helpful.
    Please share if you have any schematics.
    Please let me know.