Hi,
My customer is using this part for the power bottom trigger with below configuration, but even the clock is at falling edge, the output still change.
This does match with the truth table in the data sheet.
Abnormal waveform shown below:
Yellow: IC Pin-1 (CLK) ; Blue: IC Pin-2 (D) ; purple: IC Pin-5 (Q)
Please help to comment if there are modify needed of the configuration there are comments from your side how to deal with this problem and fix the behavior of this part.
Thanks for your help.
Hello,
I would recommend looking _much_ closer at the edges of the signals. This device responds in just a few nanoseconds, so looking at a 1s/div scale really won't show you anything.
I can see immediately that the CLK input on the SN74LVC1G74 is being subjected to extremely slow signals that need to be sped up for proper operation. From the datasheet, here's an example of the correct setup using a Schmitt-trigger buffer to clean up the slow edge from the button debounce circuit:
If this resolves your issue, please click the green "this resolved my issue" button, or if you need further assistance, please reply and I will continue to assist you.
Hi ,
thanks for your reply and i will ask RD to test with the buffer to see if there are improvement on this issue.
after zoom in to the falling edge, there are some noise at the falling edge: (condition without C174)
but after putting the C174 back:
Can you help to comment why the output still changing even there is no noise on the CLK pin?
Great thanks for your help.
Do you see how the CLK signal appears to be a DC value at the 20us time scale? This is why you are having problems.
The datasheet clearly lists the required transition rate for CLK to operate, which is 10ns/V. Your transition rate is much too slow, which causes problems for CMOS devices. This is a fundamental aspect of CMOS technology, and is the reason our application schematic in the datasheet includes a Schmitt-trigger buffer to clean up those slow edges.
Here's an FAQ that goes into some details:
Dear Emrys
We added a buffer between the button and the D Trigger in input.
But the issue is still not solved.
The input rise time is around 10ns/V now.
As shown in the snapshot below, we noticed that the input signal(u18 pin2) rised with the clock rising(positive) edge simutaneously, without any delay;
Similarly, it happens at the falling edge.
Why did they happen? How can I avoid it?
Thank you!
