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SN74LVC1G17: can SN74LVC1G17 or SN74LVC3G17 work as clock buffer?

Kazusa Suzuki
Prodigy 580 points
Part Number: SN74LVC1G17
Other Parts Discussed in Thread: SN74LVC3G17

Hello team,

I want to use SN74LVC1G17 or SN74LVC3G17 as clock buffer. Can SN74LVC1G17 or SN74LVC3G17 usually work as clock buffer?

If temprature does not change rapidly, we think input-output propagation delay is the same and output jitter does not occur or is small. could you confirm our understanding? 

If a device has multiple gates, is the delay time of each device the same?

What is the difference between a normal logic buffer and a fanout clock buffer?

Best regards,

Kazusa Suzuki

  • 0
    TI__Guru* 97046 points
    Hello Suzuki-san,
    Yes, Schmitt-trigger buffers can be used as clock buffers.

    We can only guarantee those specs provided in the datasheet. For example, with a 15pF load at 3.3V supply, the propagation delay is only guaranteed to remain within the values of 1.5ns to 4.6ns. There is no additional guarantee for jitter or variation across temperature or from part to part (process variation). The skew within a multi-channel logic device is typically less than 1ns, however that value is not guaranteed by any datasheet spec.

    Devices specifically designed as fanout clock buffers typically provide additional specifications for jitter, skew, and propagation delay. It's likely that the cost of these devices is also slightly higher due to the added testing and characterization required.

    If this answers your question, please click the green "this resolved my issue" button, and if not, please respond and I will continue to help.
  • 0 in reply to Emrys Maier
    TI__Prodigy 580 points
    Hi Emrys,

    Thank you for your answer.

    I wants to confirm one thing at last.

    >>For example, with a 15pF load at 3.3V supply, the propagation delay is only guaranteed to remain within the values of 1.5ns to 4.6ns

    Does This difference (propagation delay 1.5ns to 4.6ns) come from each device variation? Folloings are example.

    Device variation
    Device A: 3ns, device has this spec
    Device B: 2ns, device has this spec

    or
    Case 2
    Device A: 1.5ns to 4.6ns depends on H/L
    Device B: 1.5ns to 4.6ns depends on H/L

    I think case 2. just to confirm.
  • 0 in reply to Kazusa Suzuki
    TI__Guru* 97046 points
    Hello Suzuki-san,
    Neither case is correct.

    The delay from a specific CMOS logic gate changes by many factors:
    (1) Operating Voltage
    (2) Load Condition
    (3) Temperature
    (4) Process Variation (changes due to manufacturing)

    We are assuming that you are holding conditions (1) and (2) constant in your system, so the remaining changes are from either a shift in temperature, or a change during manufacturing.

    If you measure the delay of a device while holding all 4 of the above conditions constant, then the delay will be constant under those conditions.

    It's also important to note that the delay we are talking about is the larger value between tplh and tphl -- these two numbers are rarely exactly the same, but they should be pretty close since this is a balanced device.