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TXS02612: layout design guide

Shu-Cheng LIN
Guru 11785 points

Part Number: TXS02612

Hi Sirs,

Sorry to bother you.

Does TXS02612RTWR  had released layout guide? 

If yes could you help provide it?

Because we want to confirm if there any suggestion  SDIO trace length should be under than how many mil??

Thanks!!

  • 0
    TI__Guru* 97146 points
    Hi Shu-Cheng,
    There are many factors in deciding on trace length beyond just the name of the protocol. The primary concern from the TXS side is to ensure that the lines have less than 70pF of total parasitic capacitance, including all input connections on the trace.

    To determine this, you will need to know the stackup of the board (thickness of layers, permittivity, ground plane?) as well as the geometry of the trace.
  • 0 in reply to Emrys Maier
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply,

    May i know there have IBIS model can share?

    Because I am currently using the SD card is unstable, I need to bypass TXS02612 to read

  • 0 in reply to Shu-Cheng LIN
    TI__Guru* 97146 points
    Hi Shu-Cheng,
    Can you provide scope shots of the input/output of the TXS showing the instability?

    The TXS is particularly difficult to simulate due to the inclusion of one-shot drivers at each pin. Troubleshooting from the existing system is a better solution than trying to reproduce it in simulation.
  • 0 in reply to Emrys Maier
    Guru 11785 points
    Hi Sirs,
    So, no IBIS model can share? right??
  • 0 in reply to Shu-Cheng LIN
    TI__Guru* 97146 points
    No, I'm afraid that the TXS does not have an IBIS model available.
  • 0 in reply to Emrys Maier
    Guru 11785 points

    Hi Sirs,

    Pleas refer our IO waveform as below

    Have any suggest?

  • 0 in reply to Shu-Cheng LIN
    Guru 11785 points

    Hi Sirs,

    Our schematic as below

    txs02612.pdf

    The following is the length of the net

    SDIO_CK: 7588 mil
    SDIO_CMD: 7567 mil
    SDIO_D0: 7585 mil
    SDIO_D1: 7594 mil
    SDIO_D2: 7559 mil
    SDIO_D3: 7589 mil

    SD_CK: 1051 mil
    SD_CMD: 1066 mil
    SD_D0: 1108 mil
    SD_D1: 1051 mil
    SD_D2: 1089 mil
    SD_D3: 1055 mil

    M2_CK: 1040 mil
    M2_CMD: 1086 mil
    M2_D0: 1013 mil
    M2_D1: 1018 mil
    M2_D2: 1017 mil
    M2_D3: 1048 mil

  • 0 in reply to Shu-Cheng LIN
    TI__Guru* 97146 points
    Hi Shu-Cheng,
    It looks like the input clock is very poor quality, but the TXS device is still outputting a clock of the correct voltage and frequency. The out-cmd signal seems to have the worst distortion -- with the initial rising edge being lower than the final value. Is that the primary area of concern?

    For the trace lengths -- those don't really tell me much without the board stackup and other details I mentioned previously. ~8 inches of trace can definitely cause reflections and transmission line effects, but they would likely be minor for that length. I would be more concerned with the permittivity of the board and the thickness between the signal layer and the ground layer, which will let you calculate the total line capacitance.

    I can ask our translation expert to take a look at this when he gets back into town next week. He might have more insight than I do.
  • 0 in reply to Emrys Maier
    Guru 11785 points
    Hi Sirs,
    Thanks for your reply, please let us know if have any update in future.
    Thanks!!
  • 0 in reply to Shu-Cheng LIN
    TI__Guru 62990 points
    Hi Shu-Cheng,

    As Emrys suggested already, the TXS is translating the incoming signal to the output side.
    If the incoming signal is already of bad quality, the TXS may not help much at the output.
    The In clk is not 50% duty cycle, not meeting the rise time / transition time spec, and is not at ground level for the low side either.
    The out signal is actually much better than the incoming signal quality.

    You can also refer to the FAQ on the output transition rate and the effects of output loading below:
    e2e.ti.com/.../722261